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Marc Jones b6c89edb04 Improve the setup of MTRRs in stage1 to handle alignment and power of 
2 size calculations.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1133 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-15 18:12:34 +00:00
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k8 Improve the setup of MTRRs in stage1 to handle alignment and power of 2009-02-15 18:12:34 +00:00
model_fxx Setup the MTRRs in stage1 so that memory and cache are available throughout 2009-02-10 22:40:10 +00:00
stage0.S Add AP detection to stage0 to prevent APs from re-initializing mainboard setup 2009-02-10 22:41:35 +00:00