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switch-coreboot/arch/x86/amd/model_fxx
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Marc Jones a794edb17b Setup the MTRRs in stage1 so that memory and cache are available throughout 
stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF.
It also sets all system memory to WriteBack cached and sets the ROM
area to cached.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1128 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-10 22:40:10 +00:00
..
dualcore.c Finally, after two years, put in real code for stop_ap(). Code has to be 2008-09-29 14:58:56 +00:00
dualcore_id.c Finally, after two years, put in real code for stop_ap(). Code has to be 2008-09-29 14:58:56 +00:00
fidvid.c Update K8 FID/VID setup to match coreboot v2. Add support for 100MHz FIDs 2008-11-04 17:00:07 +00:00
init_cpus.c Setup the MTRRs in stage1 so that memory and cache are available throughout 2009-02-10 22:40:10 +00:00
stage1.c Finally, after two years, put in real code for stop_ap(). Code has to be 2008-09-29 14:58:56 +00:00