Commit graph

177 commits

Author SHA1 Message Date
Carl-Daniel Hailfinger
755b36f42e Add objdump and readelf to xcompile and use the results. This kills a
few hardcodes introduced with my checker.

Tested on Linux and OSX.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@798 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-22 01:22:21 +00:00
Carl-Daniel Hailfinger
b23508f4cd Make the section checker executable.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@795 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-21 19:38:32 +00:00
Carl-Daniel Hailfinger
df65052e93 v3 does not handle .data* and .bss sections in stage1 and initram. We
simply hope they are unused/empty and will get runtime crashes/
corruption/malfunction if they are not empty. Same applies to any
sections with relocation entries which can not be resolved during
link time.

Check for the emptiness of these sections and abort the build on error.
This triggers on all stage1/initram global variables which are not
declared the right way. It also triggers on local static variables.

Features of this checker:
- It doesn't only check for non-empty .data and .bss, but also for
unknown sections which would be a problem.
- It gives you the offending filename, the section and the variable
  name.
- It won't stop after the first error and will tell you about all errors
for a given file list.

This found a long-standing bug introduced in r729 and fixed in r786.
It also broke the build of every Geode target in the v3 tree because
they had multiple bugs. And it broke the build of the K8 code because
of a bug there.
Other fixes resulting from this checker are in r790 and r791.

Ron already fixed some of the bugs uncovered by this checker.

Tested for all possible variations of .data and .bss usage.

Sample output follows:
  CC      build/coreboot.initram (XIP)
  CHECK   initram (non-empty writable/allocatable sections)
build/coreboot.initram_partiallylinked.o: section .data: foo1
build/coreboot.initram_partiallylinked.o: section .bss: foo2
build/coreboot.initram_partiallylinked.o: section .data.rel.ro.local:
msrnames.2746
make: *** [build/coreboot.initram] Error 1

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Segher Boessenkool <segher@kernel.crashing.org> 


git-svn-id: svn://coreboot.org/repository/coreboot-v3@794 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-21 17:43:04 +00:00
Ronald G. Minnich
4bb450cfa3 Emergency patch so that section checker won't bounce option tables.
Also gets rid of hard-codes in fwrite for strings that might, in future,
vary.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@791 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-21 15:49:29 +00:00
Ward Vandewege
bb12df9732 Fix typo in comment:
s/addrees/address/

Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@777 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-16 13:27:05 +00:00
Carl-Daniel Hailfinger
48fe3ab5ef Current v3 code has a big problem: Shared functions.
Calling non-PIC code from PIC code needs an ABI wrapper and we don't
provide one. Our trick with function pointers is exceedingly fragile:
- it depends on gcc not being clever enough
- it forces us to compile all initram source files in one go
- parallelizing initram compilation breaks the code
- compiling one initram source file at a time breaks the code
- enabling higher optimizations breaks the code
- enabling -fwhole-program breaks the code
- declaring the function pointers const breaks the code
- it's an undocumented side effect of gcc which will go away
- we need excessively ugly shared function wrappers
- the shared function wrappers had more than their fair share of bugs
- almost nobody understands the wrappers completely
- Segher warns against them: "So why do you think this should work?
You're telling it to link PIC to non-PIC. Did you read the manual? It's
just not allowed. It cannot ever work."

Kill the SHARED wrappers and use a real ABI wrapper.
The wrapper code is autogenerated on demand.
Any function compiled into stage0 is now shared by default, yet the size
and code generation of stage0/1/2 code are unchanged. Initram code size
does decrease quite a bit and the difficulty of creating shared
functions is now zero.

The patch includes extensive documentation about the inner workings of
the new wrappers and the reasons why they look like this.

Build and boot tested on qemu.
Build tested on all targets.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Ron says:
Wow. we've need this fix for a long time.

Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@775 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-16 00:10:25 +00:00
Ronald G. Minnich
8f064580dc Emergency commit as I have broken this tool.
Basically, anything that includes files from include/ should define 
STANDALONE, so that the includes don't try to created SHARED symbols. 

This was not a problem until we made get_option SHARED. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@755 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-13 03:07:21 +00:00
Ronald G. Minnich
dbdfc77314 Add support for dtc files that end in .dtc, e.g. ide.dtc.
This is managed by stripping the .dtc from the name when it
is used to label the node in the tree.
This one's for you Peter!

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@740 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-11 16:05:53 +00:00
Carl-Daniel Hailfinger
77010a1111 The named unions in the device tree code are obnoxious and degrade
readability. Move to anonymous unions.

Build tested on all targets. Boot tested on qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Ron tested this and it boots to Linux.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@730 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-10 00:20:24 +00:00
Ronald G. Minnich
2f5d7b66a9 1. fix dtc to properly put @x,y in hex, not decimal.
2. Fix trivial bug in dtc -- ioport is 6 chars long, not 3
3. Fix all dts so that the @ parts are now in hex.
4. fix graphics mem in dbs62 to be 16 MB, per artec.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@700 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-30 15:08:25 +00:00
Carl-Daniel Hailfinger
b1596f216b Rename mainboard_part_number to mainboard_name in various places. This
is the logical continuation of r416 which happened a year ago.

As an added bonus, we now have consistent naming again, making grepping
the source for dts properties possible.

Build tested on all targets. Patch attached for Gmail users.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@697 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-20 21:05:25 +00:00
Carl-Daniel Hailfinger
a4b90bacf4 Makes mainboard-vendor naming more consistent.
mainboard-name naming has been postponed because it's not clear what the
real name should be.

Generated code is identical to the state before the patch.
Compile tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@694 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-11 12:33:46 +00:00
Carl-Daniel Hailfinger
d9e875537b Move default mainboard vendor/subsystem from Kconfig to dts.
Compile tested including boundary cases.
Runtime tested on dbe62 by Ron. Works fine.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@693 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-09 21:21:39 +00:00
Patrick Georgi
ae2520e4bd Order libraries last on the command line when
building kconfig and lxdialog, so that their
content is used to resolve unknown symbols even
when they are static libraries.

Also fix HOST_LOADLIBS typo.

Signed-Off-By: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@690 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-06-06 20:47:42 +00:00
Mart Raudsepp
58a87f61c3 doxy: Fix doxygen build by renaming Doxyfile file from .LinuxBIOS to .coreboot, as the reference in build system was already changed to Doxyfile.coreboot back in January 27th
This makes doxygen documentation building work again.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@683 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-22 15:52:33 +00:00
Ronald G. Minnich
573d88e61d The Geode has MSRs. LOTS of MSR. I get confused trying to find them.
This program was originally written for OLPC and GX, and dumps all LX
registers used in coreboot. 
I have preserved the indent structure since that gives some idea of the
scope of variables. 
Of particular interest are the GLD variables, since they are always
listed as offsets in the manuals, 
and computing the actual number (for use in rdmsr etc.) can be really
tricky. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@681 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-09 16:12:41 +00:00
Ward Vandewege
e9f7d1de66 Fix code warning - val.type is a char, and NULL is not.
Thanks to Carl-Daniel for spotting this one, and Segher for providing the solution right away.

This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@667 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-26 12:05:08 +00:00
Ward Vandewege
a53508b751 Add generic array support to the coreboot dts output code.
This is necessary for the 'unwanted_vpci' field on geode-based boards.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@661 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-17 16:13:58 +00:00
Myles Watson
c4a9590044 This very short patch fixes nrv2b compression in lar.
It also fixes lzma compression in lar to fix the silent memory
corruption that was possible when files didn't compress well.

It adds some comments to both files and the file that calls them.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@658 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-14 14:19:09 +00:00
Stefan Reinauer
12a0bfac72 fix i386-elf binutils weirdness. Thanks to Segher Boessenkool for finding this
out. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@655 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-04 23:38:51 +00:00
Stefan Reinauer
47854e08ca This adds the glibc elf.h to allow compilation on non-glibc platforms.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@652 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-04 13:10:05 +00:00
Stefan Reinauer
a8b10df926 Undo the other patches that sneaked in in my last commit.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@650 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-04 03:33:08 +00:00
Stefan Reinauer
d11478e45c This patch uses the svn version as the sublevel part of the coreboot
version string.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@648 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-04 03:29:26 +00:00
Carl-Daniel Hailfinger
5de785e23b Alvar Kusma found a bug in util/lar: If you try to add a file to a full
LAR archive, the LAR utility will segfault. This is reproduced easily by
zerofilling the LAR, then adding anything to it.

Looking at the code, the reason is obvious:
lar_empty_offset() can return an error code (-1). None of the callers
check for an error code, they simply assume the return value is valid.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@647 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-03-27 23:56:36 +00:00
Uwe Hermann
2620213302 Make util/lzma compile under gcc-4.3.0.
Signed-off-by: Klaus Schnass <dev@stuffit.at>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@646 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-03-25 19:52:13 +00:00
Myles Watson
689dad6eab This patch fixes lar options parsing, a seg fault with long path names, and
makes use of functions that were already defined.  It also adds greedy name
matching for listing and extracting archives, which allows recursive descent
into the lar directory structure.

changes file-by-file:

util/lar/lar.c:
	add more options to the usage message
	use get_larsize() instead of using larsize
	rearrange errors from parsing args to be more correct

util/lar/stream.c:
	change elfname size to MAX_PATHLEN instead of 64
	make file_in_list greedy with filename matches
	change total_size calculation to include file names
	change lar_add_entry to use header_len function instead of reinventing

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@632 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-03-05 14:51:35 +00:00
Myles Watson
66843bacbf This patch fixes lar path handling. In particular, it adds new members to the
file struct for pathname and compression, so that directories can be correctly
recursed.

file-by-file:

util/lar/lar.c:
	make error messages more verbose
	pass a pointer to the file structure instead of the name
	parse the name here with lar_process_name

util/lar/lib.c:
	change handle_directory to use a path name and respect nocompress
	change add_files to use pre-processed names
	use sensible defaults for new file members when listing or extracting
	free pathname if allocated	

util/lar/lib.h:
	add new members to struct file
	change prototypes of add_files and lar_add_file

util/lar/stream.c:
	change lar_add_file to use pathname and compression from struct file
	
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@623 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-28 14:56:43 +00:00
Myles Watson
548bf497a7 This is a simple patch which corrects directory handling for add
(makes it the same as create.)

Without this patch you can create a lar and recursively add a
directory to it, but you can't add one with add.

Another patch might be to make lar -l print something when you use the
directory option, but I'm not sure what was intended originally.

Myles

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@618 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-25 16:06:36 +00:00
Myles Watson
897ea2e08b This is a pretty trivial patch that returns an error message when the
file is not found instead of seg faulting.

test with:

lar -a coreboot.rom nonexistant_file.bin

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@615 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-21 21:02:19 +00:00
Ronald G. Minnich
61cd5ae455 This discussion is too useful to lose.
Carl-Daniel Hailfinger wrote:
> On 18.02.2008 23:55, Marc Jones wrote:
>> Carl-Daniel Hailfinger wrote:
>>> it seems that executing VSA requires vm86 to be useful. Since we
>>> unconditionally execute the VSA, we should unconditionally require 
vm86
>>> support (PCI_OPTION_ROM_RUN_VM86) via Kconfig for Geode targets. Not
>>> doing so will either cause compile failures or runtime failures.
>>>
>>> Adding
>>> select PCI_OPTION_ROM_RUN_VM86
>>> below
>>> config CPU_AMD_GEODELX
>>> did not work out for me.
>> Sorry I missed this.
>>
>> VSA requires the GDT that is in vm86.c. VSA loads similar to an 
option
>> ROM so the loader does go into VM86 mode. All the other stuff like
>> interrupt support and PCI BIOS isn't needed by VSA. I think that the
>> GDT at the top of vm86.c can be moved to a header file, gdt.h or
>> something like that.
>
> northbridge/amd/geodelx/vsmsetup.c uses
> util/x86emu/vm86.c:setup_realmode_idt() but it seems most/all of the
> setup there is not needed at all for VSA. Pulling in 
setup_realmode_idt
> pulls in the rest of vm86 through direct and indirect dependencies.
>
>> Care to make a patch? :)
>

I am also leaning towards removing the IDT for VSA init. There is a risk
if either an exception happens or a software interrupt is used you will
get unexpected results. What probably happens is that you jump off to
something that will eventually cause a triple fault and reboot. You may
think this is bad (and it is) but it is the same risk that coreboot runs
today. If coreboot had a generic IDT to handle exceptions, VSA init
would use the same IDT. Note that hardware INT (even timers) should
never happen as they are always masked.

I have built with no PCI_OPTION_ROM_RUN_VM86 and run this to filo.
- Show quoted text -

Marc







--
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones@amd.com
http://www.amd.com/embeddedprocessors

Reduce the amount of compilation errors for Geode LX targets if x86emu
or no emulation is selected instead of vm86.
Factor out GDT code from vm86.c to vm86_gdt.c
Remove IDT setup for VSA init.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-of-by: Marc Jones <marc.jones@amd.com>

This has booted to runlevel 3 and the ethernet works fine. 
Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://coreboot.org/repository/coreboot-v3@613 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-21 05:20:14 +00:00
Carl-Daniel Hailfinger
4ad45fd6c7 The commit in r558 had this:
> > Author: rminnich
> > util/x86emu/vm86.c
> > Change uses of dev_find_device to dev_find_pci_device

Unfortunately, x86emu/pcbios/pcibios.c was missed in the conversion. Fix 
it to get builds with x86emu compiling again.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@612 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-20 13:33:36 +00:00
Carl-Daniel Hailfinger
24d743968a Print name of compression algorithm in addition to the corresponding
number during boot.
Convert process_file() to use enum compalgo instead of hardcoded 
"1","2","3" and change the control structure from a series of if() 
statements to a switch() statement.

Uppercasing enum compalgo also found a name clash between NONE as 
compression algo and NONE as operation mode of util/lar.

Compile and boot tested on Qemu.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de> 


git-svn-id: svn://coreboot.org/repository/coreboot-v3@606 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-18 00:48:25 +00:00
Carl-Daniel Hailfinger
9f07a52934 On 16.02.2008 07:41, ron minnich wrote:
> Alix1c won't boot with the zero decompress code.
> I think the code is using the wrong address on decompress.

Indeed, r601 broke all targets, you were just lucky that qemu didn't
explode as well.
It's the seemingly easy patches which break booting. With your hint, I
found the bug. Myles made a small, but important mistake with the memset
for the "zeroes" decompression.
The memset zeroed the archive instead of the destination. No wonder it
did explode.
This patch fixes it and also reverts the emergency commit r604 because
that one is no longer necessary.

Ron tested on the Alix1c, boots fine, ethernet and IDE working.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@605 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-16 19:18:32 +00:00
Ronald G. Minnich
24a06158ba This is an emergency commit because the zero compression, as
it stands, is causing coreboot on the alix1c to hang. I don't know why. 

But this patch is the difference between works and hangs. I think 
the memset in the decompress is not using the right start value? Not sure. 

This simple change allows us to fix the zero decompress later, when 
we figure it out. I just lost a few hours to this and I want to make
sure the repo works before I go to bed. 

This fix tested on alix1c. Alix1c now works fine.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://coreboot.org/repository/coreboot-v3@604 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-16 06:38:45 +00:00
Ronald G. Minnich
f7ad196c0a This started out as a trivial change and turned into a big change. This
code boots and works on qemu and
alix1c. It represents a huge change and a huge improvement. There are a
few fixes left to do, which 
will come once this is in. 

This change started out easy: get the device IDs OUT of the the dts, and
into one place. We
decided the device IDs should be in the constructors ONLY. To make a
long story short, that just did 
not work out, and it revealed a flaw in the design. The result? 

- no more ids in the various dts files. 
- the constructor struct is gone -- one less struct, nobody liked the
  name anyway
- the device_operations struct now includes the device id.
- constructor property no longer used; use device_operations instead. 
- lpc replaced with ioport

All the changes below stem from this "simple" change. 

I am finding this new structure much easier to work with. I hope we're
done
on this for real, however!

TODO: 
1. Change limitation in dtc that makes it hard to use hex in pci@
notation. 

Now for the bad news. Sometime today, interrupts or io or something
stopped working between r596 and r602 -- but I did no commits at
that point. So something has gone wrong, but I don't think it's this
stuff.

I did try a build of HEAD, and it fails really, really badly. Much
more badly than this fails, so I think this commit is only going
to improve things. It does work fine on qemu, fails on alix1c, 
so I suspect one of today's "clean up commits" broke something. 


Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@603 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-16 04:13:44 +00:00
Myles Watson
2f5c48d0b2 This patch adds zero compression for bss segments. One of the reasons
for this is that currently, if you select no compression, the bss
segment of filo takes up 153K with just zeroes.  With this patch, it
always takes up a lar header + 1 byte.  I left the one byte so that
the checksum wouldn't be broken.

This patch could have taken out the calloc in the compression area,
but since it only uses compile-time memory, I decided to keep this
simple.

Myles

Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@601 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-15 19:27:13 +00:00
Myles Watson
89b00ed4f0 This patch adds dst_len for the lar uncompress functions, enabling
buffer overflow checks.  It exits with an error instead of
overflowing.

Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@594 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-13 22:15:59 +00:00
Ronald G. Minnich
4a6a5313bf The real change here is that paths can now be part of the node label
in dts. This gets rid of the ugly pcipath etc. properties. 

So, instead of

  somedevice {pcipath="1,0";};

We say pci@1,0{ etc. etc. };

As per my agreement I agree to document this in the design doc. 
The alix1c compiles but is untested, and will probably need some work. 
I will do these additional tasks on friday.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by:  Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

M    include/device/path.h
Add LPC path type, replacing SUPERIO path type, since SUPERIO is only
one type of LPC. Clean up tabbing in parts of the file (cosmetic).

M    mainboard/emulation/qemu-x86/dts
Modify this dts for the new path naming scheme.

M    device/pci_device.c
Change what used to be a BIOS_ERR (but is no longer) to a BIOS_NOTICE. 
The change is that the device tree includes more than just PCI devices, 
so finding a non-PCI device is no longer fatal; a notice is useful. 

M    device/device_util.c
Add string creation for PCI_BUS nad LPC.

M    northbridge/intel/i440bxemulation/dts
Add ID info for the chip. 

M    northbridge/intel/i440bxemulation/i440bx.c
Change initialization so it is explicitly for the .ops struct member. 

M    util/dtc/flattree.c
Add support for the new path naming scheme. 
I'm in the middle of this commit so I'll fix the hard-coded lengths 
next commit. 
Also delete dead code between #if 0 and /* and //

M    util/x86emu/vm86.c
comment out unused variables. these may someday be use, not ready
to delete them yet. 

M    Makefile
Change -O2 to -g. We need debugging on LAR far more than we need performance. 



git-svn-id: svn://coreboot.org/repository/coreboot-v3@593 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-13 21:00:20 +00:00
Myles Watson
6c88373502 This patch fixes a memory corruption error in lar when compiled on a 64-bit
architecture.  The function prototypes had a size mismatch, which overwrote
other things on the stack.  Now the prototypes use int for lengths.

Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@592 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-13 17:30:49 +00:00
Myles Watson
5383c948f8 This patch makes lar -l print a total of the bytes used in an archive.
I did it because I wanted to know the differences between preparsing
elf files and compressing the pieces. 

Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@588 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-12 20:31:42 +00:00
Ronald G. Minnich
6b4477c8cb Add a zero-fill command to lar.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


Note: the following discussion applies to this patch. 

This patch is basically limited. It is mostly useful for newly-created
LARs. 

On Feb 9, 2008 1:06 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006@gmx.net> wrote:

> If I read the code correctly, the command will try to fill the first
> occurrence of free space in the lar, not the biggest one. That means
> we
> might have to call it multiple times.

hmm. I obviously did not think of this.

> And a general problem with the code: If it finds the offset of the
> first
> empty area, it checks whether the area is big enough. If not, it does
> not search for another empty area, but returns instead with an error.

Actually, I think as written it is broken for the general case of lots
of empty spots. It should just look for the room left from start of
empty space to next LAR header. It's just that I have never had a LAR
that has more than one block of empty space, and that empty space is
always at the gap before the bootblock.

How about this. I'd like to commit now, and then fix this later, as I
really need this code in there for speed and it works fine with all
"fresh" images built with v3.

> Should we really call this "zerofill"?

"emptyfill"? I'll let it go for now but you make  good point.


> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


OK, this is clearly a work in progress but even in this form it is so
useful I'm going to commit it with a note, "This needs more work", and
with luck someone else will improve it once we need it improved -- the
basic structure is there.

Index: util/lar/stream.c
Add hlen (header len) and maxsize (max size left in lar) functions. 

Index: util/lar/lib.h
Add function prototypes and new ZEROFILL enum.

Index: util/lar/lar.c
Add -z option and command support. 



git-svn-id: svn://coreboot.org/repository/coreboot-v3@583 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-09 21:16:42 +00:00
Ronald G. Minnich
0044d53a10 This set of changes creates irq tables for alix1c and adds the functions
from v2 to install them. Linux boots fine and all interrupts
seem to work correctly -- the network comes up, USB hot plug works, 
I can mount the USB disk, etc. 

To enable pirq tables for a given mainboard, simply add the 
select PIRQ_TABLE (see below) to the Kconfig for that board. 

Again, this code builds and boots linux on the alix1c.

I think, with this change, we are very close to moving ALL LX boards to 
v3 and deprecating v2. The major remaining fix is to add an empty LAR 
entry to fill empty space in LAR and speed up the LAR file search 
process. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

Index: include/tables.h
Add prototype, conditioned on CONFIG_PIRQ_TABLE

Index: util/x86emu/vm86.c
Comment out 'debug trap' code that scribbles vectors at 0x4000. 
I don't know why this is here, but I'd like to leave it #if'ed out --
somebody, at some point, thought we needed it. To reenable, we will need
to move stage2 code or these magic vectors. 

Index: arch/x86/Makefile
Add support for conditional compilation of pirq support code. 

Index: arch/x86/pirq_routing.c
Add this file from v2. 

Index: arch/x86/archtables.c
Add call to write_pirq_routing_table (controlled by #ifdef
CONFIG_PIRQ_TABLE)

Index: arch/x86/Kconfig
Add new config variable: PIRQ_TABLE

Index: device/device.c
Fix some trivial bugs. 

Index: mainboard/pcengines/alix1c/Makefile
Add pirq table code for stage2

Index: mainboard/pcengines/alix1c/dts
Modify dts to properly set southbridge variables

Index: mainboard/pcengines/alix1c/irq_tables.c
Add code from v2 for the alix1c. 

Index: mainboard/pcengines/Kconfig
Add 'select PIRQ_TABLE'

Index: include/arch/x86/pirq_routing.h
Add include file from v2.
Remove all the SLOTCOUNT nonsense. This hack was only needed
for a very early version of gcc 3.x, where they screwed up the 
creation of struct members that used the [] syntax for variable-length
array at the end of the struct. 

Index: include/device/pci.h
Add prototype



git-svn-id: svn://coreboot.org/repository/coreboot-v3@582 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-09 16:32:59 +00:00
Carl-Daniel Hailfinger
d3a11c8953 Fix lar so that it parses .bss section headers.
This is not terribly clean but it works. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Tested with a qemu boot to work correctly.
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@580 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-08 12:15:46 +00:00
Myles Watson
2b66702db7 This patch adds support for make defconfig in v3. Those that port v3
to a board should add a defconfig in mainboard/vendor/board/defconfig.
 I think that the defconfig should:

1. Use the ROM size that comes with the board
2. Enable compression
3. Not include a payload

This will make it easy for buildrom or anyone who wants to build it
manually to use lar to add their payloads. It also allows buildrom to
keep the configs in the coreboot tree.

The patch also adds mainboard/emulation/qemu-x86/defconfig

Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@578 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-07 16:50:44 +00:00
Marc Jones
5917206641 Cache the ROM to speed up stage2 and payload decompression.
Due to some problems with PCI transactions, Geode LX needs the ROM cache properties to be write-serialize + cache disabled by runtime. More details below.

Add mainboard_pre_payload() call to each mainboard as the final coreboot function before the payload is called by stage1.

Note that this patch also grows the bootblock from 16K to 20K to make room for mainboard_pre_payload().

"The problem is a transaction depth issue and bottlenecks inside the GX
and LX that go across PCI.  The conditions are very complicated but it
comes down to we need write serialization for writes to PCI. If you
look in the data book you can't have write serialization and the cache
enabled on a given area. During coreboot we don't have to worry about
a write or a PCI bus master so I think we can enable caching the ROM.
After coreboot we can't be sure what will happen in the system so we
need to set it up to be safe. For example flashrom just clears the
write protect bit. If the cache were enabled (no write serialization)
and flashrom was writing the ROM we would be in a precarious position.
A PCI  bus master doing a read or a write that has a hit on a tag
would cause enough bottleneck conditions that it might hit the bug. We
could change flashrom but that doesn't help other tools. We need to
leave the system in a safe state. Also, caching the ROM after it is no
longer used doesn't make much sense. So, we need a call just before
the payload runs to clean up the system."

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@573 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-06 02:36:50 +00:00
Ronald G. Minnich
ce5a0d5574 with VSA operating correctly. This is tested with AMD's recently
released new-model VSA code. 


Changes:
Index: util/dtc/flattree.c
Add an ID entry for apic properties.

Index: northbridge/amd/geodelx/apic
This is a new dts for the northbridge used as an APIC.

Index: northbridge/amd/geodelx/pci
This is a new dts for the northbridge used as a PCI device.

Index: northbridge/amd/geodelx/geodelx.c
Fix a non-obvious bug: we had set phase3 scan bus for both the 
domain AND the PCI device, which is a mistake: can't scan from the 
PCI device too. 

Index: northbridge/amd/geodelx/domain
This is a new dts for the northbridge used as an pci domain.
Created via svn move dts domain

Index: device/pci_device.c
If there are leftover devices, it is now a warning, not an error, 
since there are 
some no-pci devices in the tree now. For future: only complain about
leftover PCI devices ...

Index: device/device.c
make devcnt a global and initialize it in init_dev. Add a debug printk. 

Index: mainboard/pcengines/alix1c/dts
Add an 'apic' entry for the mainboard. This actually looks pretty clean
to me, the way it went in. 

Index: northbridge/amd/geodelx/vsmsetup.c
Delete all pcibios int support, no longer needed for VSA. 

Please note that this patch includes Carl-Daniel's improvements 
below, which I have Ack-ed. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

A few minor comments. It would be great if you could address them before
committing.

northbridge/amd/geodelx/domain is a copy of northbridge/amd/geodelx/dts.
You probably want to use "svn mv" for that because it preserves history
and the old file was probably intended to have been moved, not copied.

northbridge/amd/geodelx/vsmsetup.c:247: warning: ‘biosint’ defined but
not used
Since the new VSA does not use BIOSINT services anymore, deleting
biosint and related functions from vsmsetup.c would shrink vsmsetup.c by
one fourth. Patch follows (could you merge it into your patch?):

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@571 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-02-01 20:35:53 +00:00
Ronald G. Minnich
643d952c5b In the current version of dtc, if one has the line:
/config/ = "northbridge/amd/geodelx";

Then the file northbridge/amd/geodelx/dts is read in and processed. 
Magic(TM) appends the name "/dts" to the path. 

This hack is fine with chips that only do one thing. 
But some (all) northbridge parts play several roles: APIC cluster, PCI domain
device, and PCI device. The result is a need for more than one dts, since
there are three possible devices, with three types of IDs, and so on. 

To keep things sane, I am proposing to enable multiple dts files in a
directory, names (e.g., nothing required here):
domaindts
pcidts
apicdts

(of course these names can be anything, this is just an example).
This change will require a change to the dtc, since we can no longer
assume just one dts file, and hence need a way to name these different 
files. 

The proposed change is very simple. We now require the full path name 
for the file, and eliminate the Magic(TM).

So, 
/config/ = "northbridge/amd/geodelx/pcidts";

will open the pcidts file. 
/config/ = "northbridge/amd/geodelx/domaindts";
will open the domain dts. 

Maybe we should just call it domain and pci and apic? works for me.
/config/ = "northbridge/amd/geodelx/domain";
/config/ = "northbridge/amd/geodelx/pcibridge";
/config/ = "northbridge/amd/geodelx/apic";

Changes: 
dtc.c: create a new function, fopenfile, that will only open a path if it 
really is a file. Modify dtc_open_file to use this function. fopenfile
assumes "-" means stdin; should it, or should I move that assumption back
to dtc_open_file?
dtc.h: add prototypes
dtc-parser.y: Given a config path, open the path.
southbridge/amd/cs5536/cs5536.c: example of how C code changes


Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Please see the comments below, but they do not have to be addressed for
this commit, just keep them in mind for future commits in that area.



git-svn-id: svn://coreboot.org/repository/coreboot-v3@566 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-01-29 17:48:10 +00:00
Stefan Reinauer
6220b632e7 Now version 3: LinuxBIOS -> coreboot rename.
- I left LB_TAG_ intact because they are used by the payloads
- file renames are still missing. see next commit
- some lb_ renames might be missing. feel free to provide patches.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@564 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-01-27 18:54:57 +00:00
Ronald G. Minnich
3ac5450814 This is a first cut at the implementation of VSM support. What has do be
done, long term, 
is to remove almost all of the vsmsetup.c file and use functions in the
vm86.c file.
 

The barrier to achieving that goal is the specialized nature of the vga
bios support code vs. the vsm bios support code. 
There are a few issues to resolve but what I'd like
to do is get VSA working first, then work out how to merge the rest of
the code. 

I have already done some merging at this point. 

This code does not yet work. But the board does not work either, and I 
want to get the code into the repo in case my hard drive dies.

Makefile: add vmsetup.o 

vsmsetup.c: Add this file from v2. Fix copyright and includes. 
Remove almost all assembly code in favor of code in vm86.c. 
In future, almost all code will be removed and the vm86.c code used
instead. 

vm86.c: make some assembly symbols .globl so that vsmsetup.c can use
them. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@560 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-01-24 21:54:22 +00:00
Carl-Daniel Hailfinger
68b97a6034 include/device/device.h
Remove old vendor,device struct members since we are now using the
device_id struct. 
Change declaration of dev_find_device to use device_id struct. 

device/device_util.c
Change dev_find_device to use device_id struct instead of vendor, device
parameters.
Add convenience function, dev_find_pci_device, to make it easier for
users. 

device/pci_device.c
Change uses of dev->vendor and dev->device to dev->id. 
Change prints of dev->vendor, dev->device to use the 
dev_id_string function. 

device/pci_rom.c
Change uses of dev->vendor and dev->device to dev->id. 

southbridge/amd/cs5536/cs5536.c
Change uses of dev_find_device to dev_find_pci_device

southbridge/amd/cs5536/dts
Add pciid of the cs5536

northbridge/amd/geodelx/dts
add pciid of the geodelx northbridge. 

util/x86emu/vm86.c
Change uses of dev_find_device to dev_find_pci_device

With these changes, the chipsetinit function now finds the southbridge
in the static tree, which is the first time this has worked in v3.
This success in turn means that the chipsetinit code is running for the
first time. 
We are still failing in "Finding PCI configuration type"

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@558 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-01-20 23:03:40 +00:00