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Due to some problems with PCI transactions, Geode LX needs the ROM cache properties to be write-serialize + cache disabled by runtime. More details below. Add mainboard_pre_payload() call to each mainboard as the final coreboot function before the payload is called by stage1. Note that this patch also grows the bootblock from 16K to 20K to make room for mainboard_pre_payload(). "The problem is a transaction depth issue and bottlenecks inside the GX and LX that go across PCI. The conditions are very complicated but it comes down to we need write serialization for writes to PCI. If you look in the data book you can't have write serialization and the cache enabled on a given area. During coreboot we don't have to worry about a write or a PCI bus master so I think we can enable caching the ROM. After coreboot we can't be sure what will happen in the system so we need to set it up to be safe. For example flashrom just clears the write protect bit. If the cache were enabled (no write serialization) and flashrom was writing the ROM we would be in a precarious position. A PCI bus master doing a read or a write that has a hit on a tag would cause enough bottleneck conditions that it might hit the bug. We could change flashrom but that doesn't help other tools. We need to leave the system in a safe state. Also, caching the ROM after it is no longer used doesn't make much sense. So, we need a call just before the payload runs to clean up the system." Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@573 f3766cd6-281f-0410-b1cd-43a5c92072e9 |
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