cleanups/fixes.
Fixup device tree code. Add/change methods as needed.
This should help serengeti.
Signed-off-by: Ronald G. Minnich<rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@954 f3766cd6-281f-0410-b1cd-43a5c92072e9
incorrect and incomplete pnp_dev_info[] as we did in v2.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@924 f3766cd6-281f-0410-b1cd-43a5c92072e9
some are just incomplete.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@923 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@897 f3766cd6-281f-0410-b1cd-43a5c92072e9
version, with these typos, compiled.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@889 f3766cd6-281f-0410-b1cd-43a5c92072e9
dts and making the ops struct non-static.
This is the second pass on this patch, I have put the changes in that
Uwe requested, I hope I got them all. I have not heard back from Uwe yet
but this patch is urgent.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@888 f3766cd6-281f-0410-b1cd-43a5c92072e9
mainboard that we learned with the serengeti that we needed. New
function in pnp that is for reading. new prototype in pnp.h. New
constants for ite8716f.
This board does not build yet; we are exercising code in k8 north that
the serengeti did not enable. More tomorrow.
Now that we have two boards under way we can hopefully see our way to
getting more put in. The 690 is the obvious next choice.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@876 f3766cd6-281f-0410-b1cd-43a5c92072e9
multiple links. The way this was done in v2 was a big confusing; this way is
less so.
The changes are easy. Getting them right has been hard :-)
First, for a k8 north that has three links, you can name each one as follows:
pci0@18,0
pci1@18,0
pci2@18,0
We have to have the same pcidevfn on these because that is how the k8 works.
But the unit numbers (pci0, pci1, etc.) distinguish them.
The dts will properly generate a "v3 device code"
compatible static tree that puts the links in the right place in the
data structure.
The changes to dts are trivial.
As before, dts nodes with children are understood to be a bridge.
But what if there is a dts entry like this:
pci1@18,0 {/config/("northbridge/amd/k8/pci");};
This entry has no children in the dts.
How does dt compiler know it is a bridge? It can not know unless
we add information to the dts for that northbridge part.
To ensure that all bridge devices are detected, we support the following:
if a dts node for a device has a bridge property, e.g.:
{
device_operations = "k8_ops";
bridge;
};
The dt compiler will treat it as a bridge whether it has children or not.
Why would a device not have children? Because it might be attached to a
pci or other socket, and we don't know at build time if the socket is empty,
or what might be in the socket.
This code has been tested on dbe62 and k8 simnow, and works on each.
It is minimal in size and it does what we need. I hope it resolves our
discussion for now. We might want to improve or change the device code
later but, at this point, forward motion is important -- I'm on a deadline for
a very important demo Oct. 22!
Also included in this patch are new debug prints in k8 north.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@865 f3766cd6-281f-0410-b1cd-43a5c92072e9
The individual makefiles in lib/ mainboard/ southbridge/ and superio/
have been changed accordingly and the big glue layer in
arch/x86Makefile has been modified to wrap the new rules correctly.
This pepares the way for additional optimizations during compile and
link time.
Build tested and boot tested on Qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@782 f3766cd6-281f-0410-b1cd-43a5c92072e9
readability. Move to anonymous unions.
Build tested on all targets. Boot tested on qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Ron tested this and it boots to Linux.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@730 f3766cd6-281f-0410-b1cd-43a5c92072e9
This creates a clearer distinction between source files in the source
tree we want to have compiled and indirectly created object/source files
in the object tree.
It also will make enable us to move to whole-program
optimization/compilation which should yield substantial size savings.
Then again, we may be able to do that without the makefile conversion as
well.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@714 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@712 f3766cd6-281f-0410-b1cd-43a5c92072e9
