ghetto rigged cbfs over usb using rom pointers.
bootblock uses this exclusively.
romstage copies the whole rom into sdram once that has been initialized.
ramstage uses sdram backed cbfs exclusively (since it runs on ccplex).
Some assumptions are made with respect to CONFIG_ROM_SIZE being the
actual size of the boot medium, e.g. when automatically creating an
fmap with and RW_MRC_CACHE region. With this patch the user is
warned when this is detected.
Change-Id: Ib5d6cc61ea29214d338d4c52ff799d6620a9cac7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The result is shorter and (IMHO) more readable code.
Change-Id: Ic51c05d7aa791250d775bd7a640213065d4caba0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch adds the Pmax setting in device tree. The Pmax is from
MAX(PL4_sku1, PL4_sku2, ..) + ROPmax. Given ROPmax is 30W and
the maximum PL4 is from U42, hence the Pmax = 71W + 30W = 101W.
BUG=b:72138778
BRANCH=None
TEST=USE=fw_debug emerge-nami chromeos-mrc coreboot chromeos-bootimage
& ensure the Pmax value is passed to FSP-S.
Change-Id: Ief6a134dc5b6bd2b8e07b4a44450e99ff26402d9
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
AmdInitPost returns AGESA_WARNING. This is because AGESA by default
enables bank interleaving, while the HW does not meet the requirements
for it. Disable bank interleaving, thus clearing AGESA_WARNING.
BUG=b:73118857
TEST= Build and run kahlee. Search for "agesawrapper_amdinitpost()
returned AGESA_SUCCESS".
Change-Id: Ice9270f9b10051dbb622344919223cf5439f5d7b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These typos were found through manual review and grep.
Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
GRUB2 doesn't support all architectures that coreboot supports.
Furthermore, coreboot's build script for GRUB2 doesn't support all of
these architectures.
Let the user select GRUB2 only when building for x86 and ARM, which are
known to work.
Change-Id: I5ef2020b2acb4cd008a57a2372734674f8b84a36
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Based on the pictures at http://www.fit-pc.com/web/products/intense-pc/,
the Intense PC does not look like a laptop. In its documentation it is
described as "mini-PC" or "Single Board Computer".
This patches moves the Intense-PC into the correct category on the
Supported Motherboards page.
Due to thermal considerations, I have not removed the "select
SYSTEM_TYPE_LAPTOP" in Kconfig.
Fixes: de7f8d3a19 ("mainboard/compulab: add support for CompuLab Intense-PC")
Change-Id: I4343306a2f82eed8211981cbd3b084f5d112d30b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Busybox mktemp does not support patterns with any characters after the XXXXXX
part. Drop the .o extension to make make-spike-elf.sh work on Alpine Linux.
Change-Id: I2e37ceef115c6d4d31eb617558481b2284dada83
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
These exceptions were new in the Privileged Architecture spec 1.10.
We need to delegate them to S-mode.
Change-Id: Iec15afe9656107b9aeea1677c5b8dc7d654fa746
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Update encoding.h to the version shipped with spike commit
0185d36 ("Merge pull request #165 from riscv/small_progbuf"),
and copy the license header from the LICENSE file.
Change-Id: I517042e5865986e88a589dc8623745f8d584d6b8
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The RISC-V boot protocol foresees that at every stage boundary (bootrom
to boot loader, boot loader -> OS), register a0 contains the Hart ID and
a1 contains the physical address of the Flattened Device Tree that the
stage shall use.
As a first step, pass the bootrom-provided FDT to the payload,
unmodified.
Change-Id: I468bc64a47153d564087235f1c7e2d10e3d7a658
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Due to changes in the RISC-V Privileged Architecture specification,
Linux can now be started in physical memory and it will setup its own
page tables.
Thus we can delete most of virtual_memory.c.
Change-Id: I4e69d15f8ee540d2f98c342bc4ec0c00fb48def0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
In order to support RISC-V processors with and without the RVC
extension, configure the architecture variant (-march=...) explicitly.
NOTE: Spike does support RVC, but currently doesn't select
ARCH_RISCV_COMPRESSED, because coreboot's trap handler doesn't
support RVC.
Change-Id: Id4f69fa6b33604a5aa60fd6f6da8bd966494112f
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The RISC-V Privileged Architecture spec 1.10 requires that the address part of
mtvec is four-byte aligned. The lower two bits encode a "mode" flag and should
be zero for now.
Add the necessary alignment directive before trap_entry.
Change-Id: I83ea23e2c8f984775985ae7d61f80ad75286baaa
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
... and fix them in the process.
The Kconfig help text seems to be a slightly better place for such
documentation than a comment in Kconfig.
Change-Id: I4114e17ad9c486a9de059040b0e2821540c31aad
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The ATF tegra210 platform supports more than the currently used
'tzdram_size' parameter, see plat/nvidia/tegra/include/tegra_private.h
in the ATF tree.
Add the missing parameters and set them accordingly. The passed UART id
is based on CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx, so ATF now uses the
same port for console output as coreboot.
Successfully tested with UARTB.
Change-Id: I7a47647216a154894e6c2c1fd3b304e18e85c6a5
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-on: https://review.coreboot.org/23783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Don't always set up UARTA, but instead honor
CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx and set up the clock of the
chosen UART.
Now the matching clock for the used UART is set up.
(The UART driver uses CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS, which
in return is already based on CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx.)
Change-Id: Ife209d42af83459136a019c21c2a069396ab36db
Signed-off-by: Andre Heider <a.heider@gmail.com>
Reviewed-on: https://review.coreboot.org/23796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
