Remove fsp1.1 driver code that adds vbt.bin & use soc/intel/common
instead to add vbt.bin in cbfs.
Also, VBT blob is added to CBFS as RAW type hence when walking the
CBFS to find vbt.bin, search with type as RAW.
BUG=None
BRANCH=None
TEST=None
Change-Id: Iad0cfae45889b8d209840f8627ecdad794bf7e51
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16610
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/388114
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
This implements PRW method for WLAN and configures PCIe wake pin to
generate SCI.
BUG=chrome-os-partner:56483
BRANCH=None
TEST=Suspend the system into S3 or S0ix. System should resume through wake
event from wifi.
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16611
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I9bd078c2de19ebcc652b5d981997d2a5b5f0b1b7
Reviewed-on: https://chromium-review.googlesource.com/388113
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In spd_util.c function mainboard_get_spd_data(), spd_file can
either be NULL or will point to the first byte of the SPD data,
and should not be dereferenced.
BUG=None
BRANCH=None
TEST=None
Change-Id: I1b18aea7772e4c589345d40ab02d2e871d3d067f
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16612
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/388111
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
The correct id string for gm45 is "$VBT CANTIGA ".
This can be found in the gm45 option rom:
"strings vbios.bin | grep VBT".
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16551
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c
Reviewed-on: https://chromium-review.googlesource.com/388110
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The intel x4x and gm45 have very similar integrated graphic devices.
Currently the x4x native graphic init enables VGA, while gm45 can output
on LVDS.
This patch reuses the x4x graphic initialisation code
to enable output on VGA in gm45 in a way that the behavior is similar to vbios:
If no VGA display is connected the internal LVDS screen is used.
If an external screen is detected on the VGA port it will be used instead.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16295
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391
Reviewed-on: https://chromium-review.googlesource.com/388108
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
there are two modify in the driver:
1. correctly set speeds base on DDR frequency.
Controls the speeds in the predriver circuits to reduce power.
SPEED[1:0]
2'b00:less than 800Mbps(400MHz)
2b01 : 800Mbps(400MHz) to 1600Mbps(800MHz)
2b10 : 1600Mbsp(800MHz) to 2400Mbps(1200MHz)
2b11 : 3200Mbps and greater
2. config the number of cycles phy clock pll wait time after
locking base on ddr config file.
BRANCH=none
BUG=chrome-os-partner:56940
TEST=do memtester on kevin board, and pass
Change-Id: Iabc17df37a701c4f052540c3c259f209a1db3c59
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/387428
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
It will enable PHY_PER_CS_TRAINING when DDR DDR frequency >= 666.
For per cs training, the controller should consider the PHY delay
line switch time,there should be more cycles to switch delay line.
So need increase W2W_DIFFCS_DLY_ value from 0x1 to 0x5.
BRANCH=none
BUG=chrome-os-partner:56940
TEST=do memtester on kevin board, and pass
Change-Id: I81b99cbc085769b7028e770509d79bd8d550820b
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/387506
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
for save power consumption, some gpio2 ~ gpio4 need to
set to input and pull none mode. It depend on these gpio
should shut down there power supply, so pass apio number
to ATF, to decide which gpio need to config.
BRANCH=None
BUG=chrome-os-partner:56423
TEST=run suspend_stress_test on kevin board
Change-Id: Iaf441e8e34c5591ffe7c65f6533fcf0b733ff5ac
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/378475
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
we need to disable some regulator when device into suspend,
it mean we need to pass some gpio to bl31, and disable these
gpios when bl31 run suspend function.
BRANCH=None
BUG=chrome-os-partner:56423
TEST=enter suspend, measure suspend gpio go to low
Change-Id: I03d0407e0ef035823519a997534dcfea078a7ccd
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/374046
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Colors and patters defined by UX team can be found at go/gale-hw-ui
BUG=b:31501528
TEST=Move the device to different states in FW using rec and dev
button and verify the colors
BRANCH=None
Change-Id: I95ab1fa59b483396ff1498a28f1ee98ac08d02d7
Signed-off-by: Suresh Rajashekara <sureshraj@google.com>
Reviewed-on: https://chromium-review.googlesource.com/387258
Commit-Ready: Suresh Rajashekara <sureshraj@chromium.org>
Tested-by: Suresh Rajashekara <sureshraj@chromium.org>
Reviewed-by: Christopher Book <cbook@chromium.org>
Reviewed-by: Kan Yan <kyan@google.com>
Implement postcar stage cbmem console support. The postcar stage
is more like ramstage in that RAM is already up. Therefore, in
order to make the cbmem console reinit flow work one needs the cbmem
init hook infrastructure in place and the cbmem recovery called.
This call is added to x86/postcar.c to achieve that. Additionally,
one needs to provide postcar stage cbmem init hook callbacks for
the cbmem console library to use. A few other places need to
become postcar stage aware so that the code paths are taken.
Lastly, since postcar is backed by ram indicate that to the
cbmem backing store.
BUG=chrome-os-partner:57513
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16619
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I51db65d8502c456b08f291fd1b59f6ea72059dfd
Reviewed-on: https://chromium-review.googlesource.com/386986
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The console_init(), MTRR printing, and loading ramstage
logic was previously all in assembly. Move that logic
into C code so that future features can more easily be
added into the postcar boot flow.
BUG=chrome-os-partner:57513
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16618
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I332140f569caf0803570fd635d894295de8c0018
Reviewed-on: https://chromium-review.googlesource.com/386985
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The declarations for console_init() were unconditionally
exposed even though there is a Kconfig option. Correct this
by honoring the CONFIG_POSTCAR_CONSOLE condition.
BUG=chrome-os-partner:57513
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16617
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Id45ae3d7c05a9f4ebcf85c446fc68a709513bb0f
Reviewed-on: https://chromium-review.googlesource.com/386275
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When the boot media is memory mapped mark it as cacheable
after romstage. Otherwise the boot media is uncacheable and
all loads from it take longer. Loading FSP-S alone in ramstage
went down to 17.5ms from 54ms.
BUG=chrome-os-partner:56656
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16613
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I6703334ba8fe98aca26ba1c995d6d3abb0ddef33
Reviewed-on: https://chromium-review.googlesource.com/386274
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a stripped-down version of libgnat. This is somehow comparable to
libgcc but for Ada programs. It's licensed under GPLv3 but with the
runtime library exception. So it's totally fine to link it with our
GPLv2 code and keep it under GPLv2.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/11836
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Change-Id: Ie6522abf093f0a516b9ae18ddc69131bd721dc0c
Reviewed-on: https://chromium-review.googlesource.com/386273
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some remarks on the make process:
o We usually leave Ada specs (.ads files which are like c headers)
together with the bodies (implementations in .adb files) in one
directory. So we have to know, where they live.
o If there is no matching .adb an .ads is a valid source file and
we'll generate an object file from it.
o Object files need to have the same basename as their source files :-/
That's why we put them in build/<class>/ dirs now.
o We track dependencies by looking at the compiler output (.ali files
which accompany every .o). This way we don't need any gnatmake
magic, or even more complex, less portable tools.
For ADAFLAGS_common, I simply copied the CFLAGS_common whilst dropping
everything unsupported and adding sane warning options.
The set of language features is highly restricted (see gnat.adc). This
should suit the embedded nature of coreboot and helps proving absence
of runtime errors with SPARK.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/13044
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Change-Id: I70df9adbd467ecd2dc7c5c1cf418b7765aca4e93
Reviewed-on: https://chromium-review.googlesource.com/386272
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There are certain board-specific options for reef variants. The
big one is the DPTF settings. Rearrange the ASL files such
that dsdt.asl is the main landing area. The ACPI options for
Chrome EC are contained in the variant/ec.h header so the
actual code #includes can just reside in dstd.asl. Since most
of the mainboard specific peripherals are auto generated by
the acpigen from devicetree there's no real separate need
for mainboard.asl. The one thing not addressed in this CL
is the notion of a variant having the Chrome EC or not (along
with lid, etc). Future indirection can be provided when needed
to address that requirement.
BUG=chrome-os-partner:56677
BRANCH=None
TEST=None
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16604
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I5c888f5fc64913dcff010c28f87e69ac5449e6b6
Reviewed-on: https://chromium-review.googlesource.com/386299
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
tar doesn't sort by default and takes the order of the OS which is in
most cases the order of creation. Sort by name and set influencing
environment TZ and language to be reproducible.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/16556
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Change-Id: I3d043952417000d12e81353677f1ea4aa2da4fc1
Reviewed-on: https://chromium-review.googlesource.com/386298
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
During the USB2 only mode, the Type-C PHY will be held in reset
and only USB2 part logic of USB3 OTG controller and PHY may be
used over the USB2 pins on the Type-C connector to support Low,
Full and High-speed USB operation.
BRANCH=none
BUG=chrome-os-partner:56425
TEST=Go to recovery mode, plug a Type-C USB drive containing
chrome OS image into both ports in all orientations, check if
system can boot form USB.
Change-Id: I582f04f84eef447ff0ba691ce60e9461ed31cfad
Signed-off-by: Liangfeng Wu <wulf@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/385837
Commit-Ready: Julius Werner <jwerner@chromium.org>
Tested-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Currently we are setting the gpio_tier1_sci in smihandler before
going to S3. But this won't work for S0iX as it happens from Linux
kernel and SMI handler is not involved in that flow. We need to
set this bit i.e. bit 15 in ACPI gpe0a register at 0x430h. The Linux
kernel before going to sleep checks what values are passed through
ASL as wake events (through _PRW), keeps those enabled only and
clears other bits in gpe0 enable registers. So we need to inform
the kernel to keep gpio_tier_sci also set as these are needed for
any wake event. This patch adds ASL code for sleep button device with
HID id PNP0C0E. We are adding _PRW method for sleep button device
with this patch.
BUG=chrome-os-partner:56483
BRANCH=None
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
Also from S0iX system is resuming for WIFI wake.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16564
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ie8517cad9cd37c25788c22250894d4f9db344ff9
Reviewed-on: https://chromium-review.googlesource.com/385915
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In commit 4f2754c
'fsp_broadwell_de: Add Kconfig switch for SERIRQ operation mode'
the default operation mode of SERIRQ was changed from continuous to quiet.
Set the mode to continuous for this mainboard to keep the behavior unchanged.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16576
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I7c3675d4ee8cff428621f4e64411738193e654b2
Reviewed-on: https://chromium-review.googlesource.com/385908
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fixes the warning:
Use of uninitialized value in concatenation (.) or string at
util/lint/checkpatch.pl line 4739
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16357
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Idc3c631735a595517d77cb8b8ec67e1ac00b6685
Reviewed-on: https://chromium-review.googlesource.com/385907
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This pulls in two fixes that were added to coreboot's checkpatch.pl
script:
- commit 82ef8ada (src/commonlib/lz4_wrapper: Correct inline asm for
unaligned 64-bit copy):
modify checkpatch.pl to ignore spaces before opening brackets when
used in inline assembly.
- commit ebef00fa (lint/checkpatch.pl: escape \{ in perl regex to fix
warnings):
Unescaped left brace in regex is deprecated, passed through in regex;
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16348
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Ia2c712c5b1bb5f67953a9098b5a076e31e3bd8d3
Reviewed-on: https://chromium-review.googlesource.com/385906
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
I put in the decimal values for these instead of the hex values.
Instead of running them through a BCD converter, update them to use
the hex values.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16567
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Change-Id: I3fa46f055c3db113758f445f947446dd5834c126
Reviewed-on: https://chromium-review.googlesource.com/385904
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Functionally, this should be roughly the same. The only real difference
should be removing the 4 bytes of padding from the end of the 4 byte
entries. The spec mentions a boundary for the 4 byte entries (which we
are ignoring), but doesn't mention a boundary for the 8 byte entries,
and I can't think of any other reason that the padding might be needed.
- Wrap long lines.
- Combine if statements to clean up indentation.
- Use #defines from acpi_ivrs.h to make commands easier to understand.
- Remove padding from 4 byte entries that made them 8 bytes in length.
- Set the pointer p at init, and clear the value at p if the device
we're looking at is enabled instead of setting p in every if statement.
- Look at the command type to update current and length.
- Treat malloc & free as if they were typical instead of coreboot
specific versions. Check to make sure the malloc worked and only
free on the last loop instead of every time.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16532
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Change-Id: I79dd5f9e930fad22a09d1af78f33c1d9a88b3bfe
Reviewed-on: https://chromium-review.googlesource.com/385903
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch removes setting of gpio_tier1_sci_en from mainboard
smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
now.
BUG=chrome-os-partner:56483
BRANCH=None
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
Also from S0iX system is resuming for WIFI wake.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16566
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I26fd3fd9fcc83c988bcff1bda4da7a2e3da98ce6
Reviewed-on: https://chromium-review.googlesource.com/385902
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch removes setting of gpio_tier1_sci_en from mainboard
smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
now.
BUG=chrome-os-partner:56483
BRANCH=None
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
Also from S0iX system is resuming for WIFI wake.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16565
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Change-Id: I066f0907a1c597e6fee09821910c59a8a90cccaa
Reviewed-on: https://chromium-review.googlesource.com/385901
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If FSP_M_XIP is selected, then relocate FSP-M binary
while adding it in CBFS so that it can be executed in place.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16563
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I2579e8a9be06cfe8cc162337fb1064d15842229f
Reviewed-on: https://chromium-review.googlesource.com/385899
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The TPM driver was largely ignoring the meaning of the command
ready bit in the status register, instead just arbitrarily
sending it at the end of every receive transaction.
Instead of doing this have the command ready bit be set at the
start of a transaction, and only clear it at the end of a
transaction if it is still set, in case of failure.
Also the cr50 function to wait for status and burst count was
not waiting the full 2s that the existing driver does so that
value is increased. Also, during the probe routine a delay is
inserted after each status register read to ensure the TPM has
time to actually start up.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16591
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Change-Id: I1c66ea9849e6be537c7be06d57258f27c563c1c2
Reviewed-on: https://chromium-review.googlesource.com/385897
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It is very useful to have the ability to see I2C transactions
performed by the host firmware. This patch adds a simple
Kconfig option that will enable debug output.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16590
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I55f1ff273290e2f4fbfaea56091b2df3fc49fe61
Reviewed-on: https://chromium-review.googlesource.com/385896
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change modifies the lpss_i2c driver to behave more like
the Linux kernel driver. In particular the controller is only
enabled when processing a transaction, and is disabled after.
This means that errors in one transaction will not affect later
transactions.
Also when disabling the controller the code is supposed to wait
on the enable bit in the "enable status" register and not in
the enable control register. In order to get access to this
register the reg map was expanded to include all registers.
This was tested with the cr50 TPM driver to ensure that if a
transaction does fail that it can be successfully retried instead
of the bus being unusable.
BUG=None
BRANCH=None
TEST=None
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16589
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: I43a546d54996ba0f08550a801927b8f7a6690cda
Reviewed-on: https://chromium-review.googlesource.com/385095
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch sets tuned RAPL power limit PL1 value to
12W in acpi/dptf.asl for RAPL MSR register. With PL1
as 12W for WebGL and stream case, we measured SoC power
reaching upto 6W. Above 12W PL1 value, we observed that
Soc power going above 6W. With PL1 as 12W, system is
able to leverage full TDP capacity.
BUG=chrome-os-partner:56524
BRANCH=None
TEST=Built, booted on reef and verifed the package
power with heavy workload.
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/16596
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I8185ce890f27e29bc138ea568af536bc274fe7b8
Reviewed-on: https://chromium-review.googlesource.com/385093
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
