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UPSTREAM: intel/amenia: Remove setting of GPIO_TIER1_SCI enable bit

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This patch removes setting of gpio_tier1_sci_en from mainboard
smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
now.

BUG=chrome-os-partner:56483
BRANCH=None

TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
     Also from S0iX system is resuming for WIFI wake.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16565
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>

Change-Id: I066f0907a1c597e6fee09821910c59a8a90cccaa
Reviewed-on: https://chromium-review.googlesource.com/385901
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Shaunak Saha 2016-09-09 14:50:34 -07:00 • committed by chrome-bot
parent 49d5d00b79
commit e8f5fd7970
1 changed files with 0 additions and 3 deletions
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3
src/mainboard/intel/amenia/smihandler.c
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@ -22,9 +22,6 @@
void mainboard_smi_sleep(u8 slp_typ)
{
if (slp_typ == ACPI_S3)
enable_gpe(GPIO_TIER_1_SCI);
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);