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UPSTREAM: amd/pi/hudson: Add config option for ACPI base

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Add a configuration option to assign the binaryPI base address
for the ACPI registers. The binaryPI's assignment is determine
at build time and no run-time configuration is allowed.

BUG=none
BRANCH=none
TEST=none

Change-Id: I2fa71ebe07b6d20e0d7bd9302a35c17b543c00ff
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7f2c29b6d6
Original-Change-Id: Ida17022abfa6faceb0653c2cb87aacce4facef09
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19485
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/494049
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Marc Jones 2017-04-26 21:55:03 -06:00 • committed by chrome-bot
parent 007294bc5f
commit 4fd2cefa41
2 changed files with 10 additions and 1 deletions
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9
src/southbridge/amd/pi/hudson/Kconfig
View file

@ -219,6 +219,15 @@ config SERIRQ_CONTINUOUS_MODE
help
Set this option to y for serial IRQ in continuous mode.
Otherwise it is in quiet mode.
config HUDSON_ACPI_IO_BASE
hex
default 0x400 if CPU_AMD_PI_00670F00_FP4 || CPU_AMD_PI_00670F00_FT4
default 0x800
help
Base address for the ACPI registers.
This value must match the hardcoded value of AGESA.
endif
config HUDSON_UART

2
src/southbridge/amd/pi/hudson/hudson.h
View file

@ -51,7 +51,7 @@
#define PM_YANG_SD_FLASH_CTRL 0xE8
#define PM_PCIB_CFG 0xEA
#define HUDSON_ACPI_IO_BASE 0x800
#define HUDSON_ACPI_IO_BASE CONFIG_HUDSON_ACPI_IO_BASE
#define ACPI_PM_EVT_BLK (HUDSON_ACPI_IO_BASE + 0x00) /* 4 bytes */
#define ACPI_PM1_CNT_BLK (HUDSON_ACPI_IO_BASE + 0x04) /* 2 bytes */
#define ACPI_PM_TMR_BLK (HUDSON_ACPI_IO_BASE + 0x18) /* 4 bytes */