Commit graph

19734 commits

Author SHA1 Message Date
Marshall Dawson
8bcc0790f5 UPSTREAM: amd/gardenia: Update xHCI configuration
Remove a duplicated check and setting for xHCI during the
AMD_INIT_RESET callout.  This is handled by the wrapper.  Also
remove nearby commented code.  EcChannel0 is not a member of
FCH_RESET_DATA_BLOCK.

Leave the check in AMD_INIT_ENV.  Although AGESA honors what
was previously requested, additional settings depend on the
state of Usb.Xhci0Enable.

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit ca862fbacbe80b1345ad6f23262a9769f05c50fd)

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17223
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I45a5123e158cd7399d6d286999371d4a0e0fa963
Reviewed-on: https://chromium-review.googlesource.com/422226
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 09:54:54 -08:00
Marshall Dawson
6f084b804d UPSTREAM: amd/gardenia: Configure GPIO signals
Change the default configuration for the following settings:
 AGPIO14: BT radio disable
 AGPIO64: NFC PU
 AGPIO65: NFC wake
 AGPIO66: Webcam
 AGPIO69: PCIe presence detect
 AGPIO70: GPS sleep
 AGPIO116: MUX for Power Express Eval
 EGPIO119: SD power

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit d146af183b9dbbd6bd6c7b6ad1b383bf36203da4)

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17222
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Ibbde7593f3477e30a45fd4f56f236c6e94e3725f
Reviewed-on: https://chromium-review.googlesource.com/422225
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 09:54:51 -08:00
Marshall Dawson
fbe2cc8063 UPSTREAM: amd/gardenia: Remove board ID capability
Remove the last bit of Bettong board_id checking from Gardenia.

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit b617823d1d2860a3f6d766a40ae95e5486739a5c)

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17221
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Ibc56dbbfa1b15b21ebadb9f6c9c54936566a2986
Reviewed-on: https://chromium-review.googlesource.com/422224
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 09:54:49 -08:00
Marshall Dawson
6d729527b0 UPSTREAM: amd/gardenia: Remove rev-specific storage setup
Gardenia doesn't have the ability to modify settings depending on
the board ID.

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 536b4c424e5259ddbd82469f5f426d3189ff3f89)

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17220
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I2c928431306c669735cf735042855e95721bb107
Reviewed-on: https://chromium-review.googlesource.com/422223
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 09:54:46 -08:00
Marshall Dawson
c26f69da1a UPSTREAM: amd/gardenia: Correct SPD AGESA callout
Gardenia makes no special considerations for a board_id regarding
SPD access and addressing.  Remove this from the source and use
the standard AGESA call.

Make SPD address changes to devicetree.cb.  Note that Gardenia is
designed to be a two channel, single DIMM/channel system (some SKUs
with two DIMMs on the second channel).  However, this port is for
the Stoney processor which is a single channel.  As a result, the
second DIMM slot is not usable.  A future improvement could involve
a port using a different processor, with unique devicetree files
for each.

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 77511f98f819dfe08c3ed16ebc11e1b328bdca15)

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17219
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Id00c2be83340ceeec043ec86e96779e6bf46ae7b
Reviewed-on: https://chromium-review.googlesource.com/422222
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 09:54:44 -08:00
Marc Jones
19a376b497 UPSTREAM: mainboard/amd: Copy bettong to gardenia and update for build
Use bettong as the reference for the gardenia mainboard.
Update makefiles etc so it builds.

This patch intentionlly keeps the carrizo_fch.asl file to
remain synchronized with the AMD PI package.

Remove items that do not apply to the Stoney APU, rewrite the
comments associated with the PCIe devices, and fix up the
SPD register association to match the 00670F00 chip.h.

Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit 82accfcf9ec76a042156fb6e528f7900987b6e7e)

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17218
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I014fec5c99c01fc02e129be514b704c8ba27d464
Reviewed-on: https://chromium-review.googlesource.com/422221
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 09:54:42 -08:00
Philipp Deppenwiese
35e0d58302 UPSTREAM: drivers/pc80/tpm: Set default TPM acpi path if unset
Enable default acpi path PCI0.LPCB if TPM support is
selected in the kconfig system and the acpi path is not set via
acpi_name callback in the platform code.

Thanks to Aaron Durbin for providing this fix.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/17855
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: Idb56cafe71efc8a52eee5a5a663478da99152360
Reviewed-on: https://chromium-review.googlesource.com/422220
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 09:54:39 -08:00
Patrick Georgi
fcb772c2f2 UPSTREAM: util/romcc: Don't read 'member' if it might be NULL
The earlier loop exits gracefully iff i == index. In other cases, member
might be NULL, so check that the scan was successful before using its
results.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1129147
Reviewed-on: https://review.coreboot.org/17887
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I818c233d797d82fa819243c4626dd9c4b7de3ac6
Reviewed-on: https://chromium-review.googlesource.com/422219
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 09:54:37 -08:00
Patrick Rudolph
aaa1dac5eb UPSTREAM: nb/intel/sandybridge/raminit: Separate Sandybridge and Ivybridge
Add custom files for Sandybridge and IvyBridge functions.
Move only the minimal required functions into separate files.
Both files' functions are going to call raminit_common functions.
No functionality is changed.

Sandybridge code path tested on Lenovo T420.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17605
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I1b1dfbd0857b59d3ae4392b73c033ee7a5aed243
Reviewed-on: https://chromium-review.googlesource.com/422218
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 09:54:34 -08:00
Naresh G Solanki
a1aa63681f UPSTREAM: mb/intel/kblrvp: Increase preram cbmem console size
Some part of preram cbmem console output is truncated.

Increase preram cbmem console size to 0xd00 to avoid the same.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17840
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Idbcbb3d1f433668a0e5375679f56fbe562d39ddd
Reviewed-on: https://chromium-review.googlesource.com/422217
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 09:54:32 -08:00
Naresh G Solanki
643308d5b8 UPSTREAM: x86: Configure premem cbmem console size
Sometime preram cbmem logs are truncated due to lack of
space (default preram cbmem console size is 0xc00).

Provide Kconfig option to configure preram cbmem console
size so that mainboard can configure it to required value.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17839
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I221d9170c547d41d8bd678a3a8b3bca6a76ccd2e
Reviewed-on: https://chromium-review.googlesource.com/422216
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 09:54:30 -08:00
Arthur Heymans
e82b8b6cd4 UPSTREAM: Set the fsb timer correctly for Netburst CPUs
On Netburst (Pentium 4) the fsb cannot be read from
MSR_FSB_FREQ (msr 0xcd). One has to use msr 0x2c instead.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17832
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>

Change-Id: I0beccba2e4a8ec5cd23537b2207f9c49a040fd73
Reviewed-on: https://chromium-review.googlesource.com/422215
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 09:54:27 -08:00
Furquan Shaikh
0804758ce9 UPSTREAM: drivers/i2c/generic: Allow mainboards to export reset and enable GPIOs
Add power management type config option that allows mainboards to
either:
1. Define a power resource that uses the reset and enable gpios to
power on and off the device using _ON and _OFF methods, or
2. Export reset and enable GPIOs in _CRS and _DSD so that the OS can
directly toggle the GPIOs as required.

GPIO type needs to be updated in drivers_i2c_generic_config to use
acpi_gpio type so that it can be used for both the above cases.

BUG=chrome-os-partner:60194
BRANCH=None
TEST=Verified that elan touchscreen works fine on reef using exported
GPIOs.

Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17797
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I4d76f193f615cfc4520869dedc55505c109042f6
Reviewed-on: https://chromium-review.googlesource.com/422214
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 09:54:25 -08:00
Furquan Shaikh
5e897874ed UPSTREAM: acpi_device: Add special HID for DT namespace
BUG=chrome-os-partner:60194
BRANCH=None
TEST=Compiles successfully

Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17842
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I0fe146cf2235c7c4ad3ea5589ed556884de3a368
Reviewed-on: https://chromium-review.googlesource.com/421285
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 09:54:22 -08:00
Patrick Georgi
9597841a3b UPSTREAM: util/broadcom: Check for successful file access
Change-Id: I5c77b3c5ea3fbc249a8c564a521c2c3c45e1c560
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1323510
Reviewed-on: https://review.coreboot.org/17877
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421284
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19 09:54:20 -08:00
Duncan Laurie
42df699056 UPSTREAM: google/eve: Set throttle offset to 10 degrees
Set the thermal throttle (prochot) activation to be 10 degrees
below TJmax so PROCHOT# kicks in at 90C instead of 100C.

BUG=chrome-os-partner:58666
BRANCH=none
TEST=boot on eve, check msr value before and after resume:
> iotools rdmsr 1 0x1a2
0x000000000a6400e6
> echo mem > /sys/power/state
> iotools rdmsr 1 0x1a2
0x000000000a6400e6

Original-Change-Id: I3ab3a050a1e27c18a940bd7519eabaf015ef93eb
Original-signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-reviewed-on: https://review.coreboot.org/17901
Original-tested-by: build bot (Jenkins)
Original-reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I520f8224c006b94c6a20d7d7dac1768b17cd0c45
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/422076
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-17 14:43:51 -08:00
Julius Werner
50ff17107d rockchip/common: Loosen I2C frequency target requirements
I've recently added an assertion to ensure that the effective I2C
frequency on Rockchip SoCs is not too far off the 400KHz target due to
divisor rounding errors. A 10KHz margin worked fine for RK3399, but it
turns out that RK3288 actually only ever hit 387KHz since its I2C clocks
are based off the already pretty low 75MHz PCLKs. While we could
probably change the PCLKs to make this closer, that seems like a too
intrusive change for something that has already worked just fine for
years, so just loosen the restriction a little more instead.

BRANCH=None
BUG=chromium:675043
TEST=None

Change-Id: I7e96a1a75b38f8ad3971dd33046699cceb17b80d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421095
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2016-12-17 02:01:09 -08:00
Patrick Georgi
e225821693 UPSTREAM: samsung/exynos5420: Fix test for src < 0
It was unsigned, not a good place to be for testing < 0.

Change-Id: I126fe86422900bbae2c3ca16052be27985cfed53
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Found-by: Coverity Scan #1241911
Original-Reviewed-on: https://review.coreboot.org/17888
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Tested-by: build bot (Jenkins)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421220
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2016-12-16 15:42:11 -08:00
Patrick Georgi
bd3c7e71f8 UPSTREAM: util/romcc: remove self-assignment
Change-Id: I0f78b55b28011cdefc90665bca2a7ea17647e955
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Found-by: Coverity Scan #1129127
Original-Reviewed-on: https://review.coreboot.org/17885
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421219
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2016-12-16 15:42:09 -08:00
Patrick Georgi
7cd937c15c UPSTREAM: util/romcc: Move access after NULL-check
Change-Id: I7f9c38fd6e75b32fe1ed8a60c7054f4dd1fcd5c0
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Found-by: Coverity Scan #1129104
Original-Reviewed-on: https://review.coreboot.org/17884
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421218
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2016-12-16 15:42:06 -08:00
Patrick Georgi
7c655b3316 UPSTREAM: util/romcc: Fix resource leak
Change-Id: I0d260254bab714ec939fc199b3a133b0fc05b10d
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Found-by: Coverity Scan #1129112
Original-Reviewed-on: https://review.coreboot.org/17883
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421217
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2016-12-16 15:42:04 -08:00
Patrick Georgi
02ba75a7c6 UPSTREAM: util/broadcom: Add two more NULL checks
Change-Id: I088730fd87dd39fa2c36a06c5770fad05a5808b0
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Found-by: Coverity Scan #1323511, #1323512
Original-Reviewed-on: https://review.coreboot.org/17882
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421216
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2016-12-16 15:42:01 -08:00
Patrick Georgi
07f561c2cb UPSTREAM: util/broadcom: Check return value of stat()
Change-Id: Ib53408e8b186c07aa8e42c67131d39c4add05983
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Found-by: Coverity Scan #1323515
Original-Reviewed-on: https://review.coreboot.org/17881
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421215
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2016-12-16 15:41:59 -08:00
Patrick Georgi
33b86a139c UPSTREAM: util/broadcom: Initialize variable
It's later tested for NULL, but never initialized to make that test work
reliably.

Change-Id: Iadee1af224507a6dd39956306f3eafa687895176
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Found-by: Coverity Scan #1323515
Original-Reviewed-on: https://review.coreboot.org/17880
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421214
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2016-12-16 15:41:57 -08:00
Patrick Georgi
066676b4da UPSTREAM: util/broadcom: Close file after use
Change-Id: Ieea7ac7fbc618cd12f843f1606f9ebab37cae67e
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Found-by: Coverity Scan #1323508
Original-Reviewed-on: https://review.coreboot.org/17879
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421213
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2016-12-16 15:41:54 -08:00
Patrick Georgi
bcefbf84ce UPSTREAM: util/broadcom: Terminate string
filebuffer is treated like a string, so it should be zero-terminated
like a string.

Change-Id: I078aa39906394be64023424731fe0c7ae2019899
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Found-by: Coverity Scan #1323473
Original-Reviewed-on: https://review.coreboot.org/17878
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421212
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2016-12-16 15:41:52 -08:00
Patrick Georgi
c35186c9aa UPSTREAM: util/broadcom: close file on error
Change-Id: I5193c6a9f08398b881c971c7175654ba5775b34a
Original-Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Found-by: Coverity Scan #1323509
Original-Reviewed-on: https://review.coreboot.org/17876
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421211
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2016-12-16 15:41:49 -08:00
Duncan Laurie
cfac7a5573 UPSTREAM: google/eve: Enable touch devices
Enable the actual touch devices to be probed by the kernel
and remove the placeholder devices that I put in before
and were used for initial bringup.

BUG=chrome-os-partner:58666
TEST=tested on eve

Change-Id: I7fc6f9da83b1abbae6dd069f759b220d59153d1c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/17896
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421210
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2016-12-16 15:41:47 -08:00
Vadim Bendebury
de2011dad7 UPSTREAM: tpm2: handle failures more gracefully
When trying to bring up a device with a malfunctioning TPM2 chip, the
driver currently gets stuck waiting for SPI flow control, causing
bricked devices.

This patch puts a 100 ms cap on the waiting time - this should be
enough even for a longest NVRAM save operation which could be under
way on the TPM device.

BRANCH=gru
BUG=chrome-os-partner:59807
TEST=with a matching change in depthcharge, now a gru with corrupted
SPI TPM comes up to the recovery screen (it was not showing signs
of life before this change).

Change-Id: I63ef5dde8dddd9afeae91e396c157a1a37d47c80
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/17898
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: build bot (Jenkins)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/421209
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
2016-12-16 15:41:44 -08:00
Duncan Laurie
1bad66844c UPSTREAM: google/eve: Enable native mode for UART pins in bootblock
Put the UART pins into native mode in bootblock so they are not
floating when we try to communicate with H1 over I2C.  Without
a serial console enabled BIOS these pins were not configured
until ramstage.

BUG=chrome-os-partner:60935
BRANCH=None

TEST=Boot Eve board without serial console and H1 TPM enabled

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I30f3bf0bacc1bbd776b351a9c09748b0601c39bc
Reviewed-on: https://chromium-review.googlesource.com/421173
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 07:51:57 -08:00
Duncan Laurie
d535a32c87 UPSTREAM: drivers/i2c/hid: Add generic I2C HID driver
Add a generic I2C-HID driver for these types of devices that
do not need extra functionality.  This allows a new device to
be added without having to write a new driver.

The i2c-hid PNP0C50 is automatically added as the _CID for the
device in the ACPI Device.

BUG=chrome-os-partner:58666
BRANCH=None

TEST=used on eve to describe a new i2c-hid touch controller

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Change-Id: I94e9531a72f9bf1d6b3ade362b88883b21b83d0a
Reviewed-on: https://chromium-review.googlesource.com/421172
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 07:51:54 -08:00
Dennis Wassenberg
36c5309f83 UPSTREAM: mb/roda/rv11: Add new boards Lizard RV11 and RW11
The Roda Lizard RV11 is a comparatively lightweight, full-rugged
notebook. It's based on a 17W TDP dual core Ivy Bridge CPU.

The Lizard RW11 is its bigger brother (45W TDP quad core, more i/o
options).

The RV11 is the first board to use the native graphics initialization
by libgfxinit. Tested so far, are the internal eDP port, DP and VGA.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17446
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Iea283059ce3402dc36184baf16928b55285a9eeb
Reviewed-on: https://chromium-review.googlesource.com/421171
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 07:51:52 -08:00
Nico Huber
972b500cd8 UPSTREAM: util/ifdfake: Add number of regions
To make the generated descriptor compatible with latest libflashrom.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17447
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

Change-Id: I005159dd24e72da9cc43119103c96c5dd5b90a55
Reviewed-on: https://chromium-review.googlesource.com/421170
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 07:51:49 -08:00
Arthur Heymans
2b00b680f3 UPSTREAM: mb/ga-945gcm-s2l: Fix resume from suspend
Checking for memory self refresh can generate false positives,
as explained in faa6beb: "northbridge/intel/i945:
CHECK_SLFRCS_ON_RESUME Kconfig option".

This seems to be the case for this motherboard.

TESTED on ga-945gcm-s2l.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17617
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: Iadf0a73b054470b652e1dc02557fb1715131f823
Reviewed-on: https://chromium-review.googlesource.com/421169
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 07:51:47 -08:00
Matt DeVillier
cb5b3a3eb6 UPSTREAM: smbios.h: add missing SKU field to type3 table
The type3 SMBIOS table has a non-optional SKU field at the end,
which causes a parsing error when missing.  Add but do not populate it.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17851
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I988d0626b8680740697e1db58eb6d0b87874bfde
Reviewed-on: https://chromium-review.googlesource.com/421168
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 07:51:45 -08:00
Matt DeVillier
79d89b1369 UPSTREAM: ec/ene932: correct ACPI battery data fed into ToString()
ToString() requires the input buffer data to be null-terminated,
but the data returned by the EC is not, leading Windows to fail
to report any battery data at all.  Correct this by concatenating
a null terminator (0x00) to the end of the buffer data before
inputting to ToString() where needed

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17783
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>

Change-Id: Ic86048d1d6354b9b0dac3c8957df318d0825c905
Reviewed-on: https://chromium-review.googlesource.com/421167
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 07:51:42 -08:00
Aaron Durbin
034bb73b28 UPSTREAM: mainboard/google/reef: clear normal MRC cache on recovery retrain
For Chrome OS the normal MRC cache should be cleared when a hardware
retrain recovery request is observed. The reason is that since there
are 2 different MRC cache slots there needs to be a mechanism which
allows an end user make a system bootable again if the MRC settings
happen to not allow the system to boot any longer. Therefore, one
just needs to enter recovery with the hardware retrain flag and
the system normal MRC cache slot will be invalidated.

BUG=chrome-os-partner:60592
BRANCH=reef
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17871
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

Change-Id: I6ad32ed0dd217d66404b77467a88689a06044544
Reviewed-on: https://chromium-review.googlesource.com/421030
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 07:51:40 -08:00
Aaron Durbin
87b5af6501 UPSTREAM: soc/intel/common: provide option to invalide MRC cache on recovery
Allow a board/platform to invalidate the normal MRC cache when
hardware retraining is requested in recovery mode. A small 4 byte
payload is used to update the latest data written. It will of course
fail on MRC cache retreival on next usage.

BUG=chrome-os-partner:60592
BRANCH=reef
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17870
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: Ic88cd66802664813562d003f50d54e4a4ea375ef
Reviewed-on: https://chromium-review.googlesource.com/421029
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 07:51:38 -08:00
Aaron Durbin
dd311e048a UPSTREAM: ec/google/chromeec: query cbmem for retrain status
The EC switches, including the hardware retrain flag, are
cleared when handing off the vboot state in romstage. However,
one may still want to query the state of the hardware retrain
flag. Thus, add a method to get the flag from cbmem.

BUG=chrome-os-partner:60592
BRANCH=reef
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17869
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

Change-Id: Ic76cfb3255a8d3c179d5f8b13fa13c518f79faa2
Reviewed-on: https://chromium-review.googlesource.com/421028
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 07:51:35 -08:00
Aaron Durbin
d3937f59c3 UPSTREAM: lib/cbmem: allow anyone to use cbmem_possibly_online()
The cbmem_possibly_online() is a helpful construct. Therefore,
push it into cbmem.h so other users can take advantage of it.

BUG=chrome-os-partner:60592
BRANCH=reef
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17868
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: If5a1c7815ed03874dcf141014b8ffefb82b7cc92
Reviewed-on: https://chromium-review.googlesource.com/421027
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 07:51:33 -08:00
Aaron Durbin
2bdc57b886 UPSTREAM: soc/intel/apollolake: don't probe flash manually
Rely on boot_device_spi_flash() to provide the spi_flash
object. There's no need to duplicate the probing logic.

BUG=chrome-os-partner:56151
BRANCH=reef
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17867
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

Change-Id: I91900a3dfad7ba92cbd3b0ace77b08db04cff0b6
Reviewed-on: https://chromium-review.googlesource.com/421026
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 07:51:31 -08:00
Patrick Georgi
4e42a37159 UPSTREAM: util/cbfstool: Handle error condition more carefully
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1295494
Reviewed-on: https://review.coreboot.org/17861
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)

Change-Id: I72a7776d530d1cf0b8fa39e558990df3dc7f7805
Reviewed-on: https://chromium-review.googlesource.com/420522
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 07:51:28 -08:00
Patrick Georgi
f1a1abee6d UPSTREAM: util/cbfstool: check that buffer_create worked
We might not care much about this buffer, but we really use it later
on...

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1294797
Reviewed-on: https://review.coreboot.org/17860
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)

Change-Id: Ia16270f836d05d8b454e77de7b5babeb6bb05d6d
Reviewed-on: https://chromium-review.googlesource.com/420521
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 07:51:26 -08:00
Patrick Georgi
90b1aa14f8 UPSTREAM: util/cbfstool: Fix memory leak
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1325836
Reviewed-on: https://review.coreboot.org/17859
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I66cb1c88155ef58610bacfb899e0132e4143c7ac
Reviewed-on: https://chromium-review.googlesource.com/420520
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 07:51:24 -08:00
Patrick Georgi
06b470b633 UPSTREAM: util/cbfstool: Add NULL-ptr check
BUG=None
BRANCH=None
TEST=None

Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1323507
Reviewed-on: https://review.coreboot.org/17858
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I8b5caf5423135fe683a24db6700b895a2685cb98
Reviewed-on: https://chromium-review.googlesource.com/420519
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 07:51:21 -08:00
Martin Roth
0e4272c74e UPSTREAM: google/reef: Remove VARIANT_DIR definition
VARIANT_DIR is defined in coreboot/Makefile.inc, so doesn't need to be
defined in each mainboard.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17841
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: Ic93957b710e4a9863774de7fcf3bd006696b6aa1
Reviewed-on: https://chromium-review.googlesource.com/421006
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 04:51:17 -08:00
Furquan Shaikh
dc8acb5a77 UPSTREAM: drivers/i2c: Pass in i2c_generic_config into i2c_generic_fill_ssdt
Remove any assumptions required for the drivers using i2c_generic to
have drivers_i2c_generic_config structure at the start of the driver
config. Instead pass in a pointer to drivers_i2c_generic_config from
the calling driver.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17857
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)

Change-Id: I51dc4cad1c1f246b51891abf7115a7120e87b098
Reviewed-on: https://chromium-review.googlesource.com/420845
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 04:51:15 -08:00
Matt DeVillier
16faa4cf0b UPSTREAM: ec/chromeec: Correct ACPI battery data fed into ToString()
ToString() requires the input buffer data to be null-terminated,
but the data returned by the EC is not, leading Windows to fail
to report any battery data at all.  Correct this by concatenating
a null terminator (0x00) to the end of the buffer data before
inputting to ToString().

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17782
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I4fdbf97e9b75030374dffc99a954dd9faa6a5209
Reviewed-on: https://chromium-review.googlesource.com/420844
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 04:51:12 -08:00
Aaron Durbin
4e1c68b657 UPSTREAM: soc/intel/common: remove mrc cache assumptions
Update the mrc cache implementation to use region_file. Instead
of relying on memory-mapped access and pointer arithmetic
use the region_devices and region_file to obtain the latest
data associated with the region. This removes the need for the
nvm wrapper as the region_devices can be used directly. Thus,
the library is more generic and can be extended to work on
different boot mediums.

BUG=chrome-os-partner:56151
BRANCH=None
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17717
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: Ic14e2d2f7339e50256b4a3a297fc33991861ca44
Reviewed-on: https://chromium-review.googlesource.com/420843
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 04:51:10 -08:00
Werner Zeh
dc75b6a1d5 UPSTREAM: pcf8523: Fix wrong initialization of several registers
In the case where the RTC is initialized after the battery is
completely drained the bits for power_mode and cof_selection are set up
with wrongly applied masks.
In the case where the RTC is re-initialized again with no power-loss
after the last initialization the bits for cap_sel, power_mode and
cof_selection are not shifted to the right position.

Both errors lead to a wrong initialization of the RTC and in turn to a
way larger current consumption (instead of 120 nA the RTC current rises
to over 2 A).

This patch fixes both errors and the current consumption is in the right
range again.

TEST=booted mc_bdx1 and verified current consumption of RTC

BUG=None
BRANCH=None

Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/17829
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: I8594f6ac121a175844393952db2169dbc5cbd2b2
Reviewed-on: https://chromium-review.googlesource.com/420842
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
2016-12-16 04:51:07 -08:00