Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

UPSTREAM: google/eve: Enable native mode for UART pins in bootblock

Browse source 
Put the UART pins into native mode in bootblock so they are not
floating when we try to communicate with H1 over I2C.  Without
a serial console enabled BIOS these pins were not configured
until ramstage.

BUG=chrome-os-partner:60935
BRANCH=None

TEST=Boot Eve board without serial console and H1 TPM enabled

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

Change-Id: I30f3bf0bacc1bbd776b351a9c09748b0601c39bc
Reviewed-on: https://chromium-review.googlesource.com/421173
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Duncan Laurie 2016-12-14 16:57:37 -08:00 • committed by chrome-bot
parent d535a32c87
commit 1bad66844c
1 changed files with 4 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/mainboard/google/eve/gpio.h
View file

@ -225,6 +225,10 @@ static const struct pad_config early_gpio_table[] = {
/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TPM */
/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* TPM_INT_L */
/* Ensure UART pins are in native mode for H1 */
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
};
#endif