Commit graph

208 commits

Author SHA1 Message Date
Myles Watson
9d6d811dd1 This patch converts __FUNCTION__ to __func__, since __func__ is standard.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1131 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-12 21:15:34 +00:00
Pattrick Hueper
4c7a76da2e YABEL: (trivial) add BSD license header to files missing a license header
Signed-off-by: Pattrick Hueper <phueper@hueper.net>
Acked-by: Pattrick Hueper <phueper@hueper.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1102 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-01-07 09:14:03 +00:00
Uwe Hermann
9fce7f464a Add missing BSD license header to the PMM files.
Signed-off-by: Pattrick Hueper <phueper@hueper.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1101 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-01-06 00:05:45 +00:00
Myles Watson
54f58ebae7 Subject: [PATCH] YABEL: add PMM functionality.
Signed-off-by: Pattrick Hueper <phueper@hueper.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1086 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-23 19:21:54 +00:00
Myles Watson
93ced1cbd1 Subject: [PATCH] YABEL: small cleanup fixes
remove Makefile in yabel directory, since it is not needed (leftover
 from SLOF biosemu)
 fix dump() function output to not include \r

Signed-off-by: Pattrick Hueper <phueper@hueper.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1082 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-22 17:36:06 +00:00
Myles Watson
a94ea6f062 Date: Sun, 21 Dec 2008 00:09:12 +0100
Subject: [PATCH] use the rom_addr passed by coreboot, needed for ROM images from LAR

Signed-off-by: Pattrick Hueper <phueper@hueper.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1081 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-22 17:27:00 +00:00
Myles Watson
5227098e16 This patch removes the logic for multiple links. It would put siblings that
were bridges as separate links.  There isn't a board in v3 that needs multiple
links yet.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1079 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-19 02:40:54 +00:00
Myles Watson
80aa586a51 Subject: [PATCH 4/5] integration of biosemu (aka YABEL) into coreboot
Signed-off-by: Pattrick Hueper <phueper@hueper.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1076 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-16 22:46:55 +00:00
Myles Watson
755783fa42 Subject: [PATCH 3/5] fix build warnings in x86emu, especially with -DDEBUG
Signed-off-by: Pattrick Hueper <phueper@hueper.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1075 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-16 22:42:58 +00:00
Myles Watson
0b31c2f3b2 Subject: [PATCH 2/5] x86emu changes from slof-JX-1.0.7-4
implemented bswap opcodes, some tracing fixes, small bugfixes

Signed-off-by: Pattrick Hueper <phueper@hueper.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1074 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-16 22:42:05 +00:00
Myles Watson
20f7182ce6 Subject: [PATCH 1/5] original biosemu version, from slof-JX-1.7.0-4
Signed-off-by: Pattrick Hueper <phueper@hueper.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1073 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-16 22:40:27 +00:00
Myles Watson
12a3094274 This patch makes subsystem ids work. Here are the changes by file:
device/pci_device.c:
    Only update IDs if:
    - The device is on the mainboard
    - The device has a Vendor ID and Device ID
    - The device has a set_subsystem function in ops_pci(dev)

util/dtc/flattree.c:
    Make devices from the dts be on_mainboard.
    If they're plugged in, they shouldn't be in the dts.

mainboard/amd/serengeti/dts:
    Add subsystem_vendor and subsystem_device.

Build tested on Serengeti.  Getting closer :)

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1045 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-19 03:05:33 +00:00
Carl-Daniel Hailfinger
0153293887 Not a single file is being rebuilt in v3 if build.h changes. That means
the console banner and the option table will never be updated with more
recent build.h strings.

Thanks to Mart Raudsepp for spotting this oddness.

x86emu doesn't care about the contents of build.h, it just uses build.h
to check whether it is compiled in conjunction with coreboot.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1036 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-16 22:59:52 +00:00
Mart Raudsepp
705439d7aa Fix a build error when using bison-2.4
This fixes one of the errors from using bison-2.4, but there are more.

This one in details is the following error:

  BISON   build/util/dtc/dtc-parser.tab.c
  HOSTCC  build/util/dtc/dtc-parser.tab.o
/home/leio/dev/coreboot-v3/util/dtc/dtc-parser.y: In function ‘yyuserAction’:
/home/leio/dev/coreboot-v3/util/dtc/dtc-parser.y:154: error: expected ‘;’ before ‘}’ token
make: *** [/home/leio/dev/coreboot-v3/build/util/dtc/dtc-parser.tab.o] Error 1

Note that 2.4.1 might be made to still work without the semi-colon for some languages, but I
understand 2.5 then still won't work without one. As it builds fine with this change with
bison-2.3, it should be safe to just add the semicolon.

The remaining error is the following:

/home/leio/dev/coreboot-v3/util/dtc/dtc-lexer.l: In function ‘yylex’:
/home/leio/dev/coreboot-v3/util/dtc/dtc-lexer.l:73: error: ‘yylval’ undeclared (first use in this function)
/home/leio/dev/coreboot-v3/util/dtc/dtc-lexer.l:73: error: (Each undeclared identifier is reported only once
/home/leio/dev/coreboot-v3/util/dtc/dtc-lexer.l:73: error: for each function it appears in.)

dtc-parser.tab.h doesn't seem to get an "extern YYSTYPE yylval" declaration, which per documentation should
only happen for pure parser cases ("%define api.pure"), but I can't find any such declaration in dtc to cause
the problem.

Note that upstream dtc builds fine with bison-2.4

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1004 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-12 17:04:15 +00:00
Carl-Daniel Hailfinger
ee7668d654 r965 broke x86emu compilation on all v3 targets.
Fix the issue. OBJ->SRC conversions are a bit tricky to get right.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@989 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-09 01:03:57 +00:00
Carl-Daniel Hailfinger
9bf25a9c08 Every time we run make in a v3 tree, lar, lzma, nrv2b and the option
table get rebuilt unconditionally due to slightly incorrect
dependencies.
That's wasteful and may hide other dependency bugs.
Fix the lar, lzma, nrv2b and option table dependencies.

This trims down recompilation time a lot. The only remaining stuff being
rebuilt is:
~/corebootv3-better_dependencies> make
  CP      build/config.h
  GEN     build/build.h
  LAR     build/coreboot.rom
  PAYLOAD none (as specified by user)
  CP      build/bios.bin
  DONE

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@984 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-06 13:59:14 +00:00
Ronald G. Minnich
2e15399b56 Yank out splashscreen support -- that is for seabios.
Signed-off-by: Ronald G. Minnich <rminnich@gmai.com>
Acked-by: Ronald G. Minnich <rminnich@gmai.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@970 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-31 18:39:46 +00:00
Ronald G. Minnich
cfa4c50225 This is the beginning of support for saving base registers that already have a v
alue. There 
is a known bug in v2/v3 wherein a BAR that is set is ignored. This change will c
ome in very
slowly as it is a bit tricky to get right as we redesign the dev code.

Also make the vm86 stuff use the SRC instead of OBJ names so we can see it in ks
cope. 

Finally, beginnings of documentation changes, not finished yet. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@965 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-31 17:40:01 +00:00
Myles Watson
eece345b2c This patch makes the vm86 call succeed. It
1. moves the run_bios function down so it can call setup_realmode_idt
2. adds the __attribute__((regnum(0))) to biosint because it is called from assembly

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@964 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-29 20:39:32 +00:00
Myles Watson
b04f94ae37 White space cleanup in vm86.c so that the next patch is more readable.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@962 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-29 18:12:22 +00:00
Uwe Hermann
9b90a6f22b Fix a bunch of Doxygen warnings in v3 (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@951 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-23 18:55:01 +00:00
Ronald G. Minnich
36d976d16c Allow setting of rom_address where needed.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@938 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-20 15:21:19 +00:00
Myles Watson
8b2f6c4c4a Change statictree emit function to emit path correctly for cpus.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@931 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-15 17:46:52 +00:00
Ronald G. Minnich
371f3e67ce I need this to get my work done and there were no better proposals.
I did change the /bin/bash to /bin/sh per the comments. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@919 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-13 18:38:50 +00:00
Ronald G. Minnich
28ecbeab88 The K8 is one example, but there are other devices (e.g. I2C) that also have
multiple links. The way this was done in v2 was a big confusing; this way is 
less so. 

The changes are easy. Getting them right has been hard :-)

First, for a k8 north that has three links, you can name each one as follows:
pci0@18,0
pci1@18,0
pci2@18,0

We have to have the same pcidevfn on these because that is how the k8 works. 
But the unit numbers (pci0, pci1, etc.) distinguish them. 

The dts will properly generate a "v3 device code" 
compatible static tree that puts the links in the right place in the 
data structure. 

The changes to dts are trivial. 
As before, dts nodes with children are understood to be a bridge. 
But what if there is a dts entry like this:
pci1@18,0 {/config/("northbridge/amd/k8/pci");};


This entry has no children in the dts. 
How does dt compiler know it is a bridge? It can not know unless 
we add information to the dts for that northbridge part. 
To ensure that all bridge devices are detected, we support the following: 
if a dts node for a device has a bridge property, e.g.: 
 {
        device_operations = "k8_ops";
       bridge;
 };

The dt compiler will treat it as a bridge whether it has children or not. 

Why would a device not have children? Because it might be attached to a
pci or other socket, and we don't know at build time if the socket is empty, 
or what might be in the socket. 

This code has been tested on dbe62 and k8 simnow, and works on each. 
It is minimal in size and it does what we need. I hope it resolves our 
discussion for now. We might want to improve or change the device code
later but, at this point, forward motion is important -- I'm on a deadline for
a very important demo Oct. 22!

Also included in this patch are new debug prints in k8 north. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@865 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-17 16:36:20 +00:00
Carl-Daniel Hailfinger
c2084e9de3 I managed to break dtc while working on PCI bridges:
dtc only uses dev_fn as identifier for a PCI device. That gets us a name
collision if we have the same dev_fn combination on multiple buses.
Either we add a random unique ID to the struct name or we integrate the
path to the parent device as well.
I decided to go for integration of parent device path.

With the following device tree

/{
        cpus {};
        domain@0 {
                bus@0 {
                        pci@0,0 {
                        };
                        pci@1,1 {
                        };
                        pci@f,0 {
                                bus@1 {
                                        pci@0,0 {
                                        };
                                };
                        };
                };
        };
};


we get the old names:
dev_root
dev_cpus
dev_domain_0
dev_bus_0
dev_pci_0_0
dev_pci_1_1
dev_pci_f_0
dev_bus_1
dev_pci_0_0 COLLISION!!!

and the new names:
dev_root
dev_cpus
dev_domain_0
dev_domain_0_bus_0
dev_domain_0_bus_0_pci_0_0
dev_domain_0_bus_0_pci_1_1
dev_domain_0_bus_0_pci_f_0
dev_domain_0_bus_0_pci_f_0_bus_1
dev_domain_0_bus_0_pci_f_0_bus_1_pci_0_0

Ron would like shorter names because they only have to be
machine-readable. That's left for another patch.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@860 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-06 20:39:25 +00:00
Carl-Daniel Hailfinger
d2d95b25cc The .next pointer was written twice for every struct device in
statictree.c. This bug was introduced in r175.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@859 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-06 20:30:26 +00:00
Carl-Daniel Hailfinger
5e4770fc02 Prepare for per-device subsystem IDs.
Fix the bus location for Qemu IDE.

This patch only provides the needed infrastructure for per-device
subsystem IDs, it does not hook them up to the PCI core yet, so this
patch is a no-op.
By the way, the on_mainboard property is activating lots of completely
untested code paths in v3, so someone might want to audit them.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@844 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-29 08:49:24 +00:00
Stefan Reinauer
87adbc377b small dependency fix, plus make oldconfig & co need libintl, too :)
(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@842 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-28 22:44:49 +00:00
Carl-Daniel Hailfinger
2b9919965b Fix a type warning in printf.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@819 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-24 18:20:31 +00:00
Ronald G. Minnich
c499c2c6bb This now builds a K8 bios image.
Now to start testing.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@810 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-24 06:07:21 +00:00
Carl-Daniel Hailfinger
755b36f42e Add objdump and readelf to xcompile and use the results. This kills a
few hardcodes introduced with my checker.

Tested on Linux and OSX.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@798 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-22 01:22:21 +00:00
Carl-Daniel Hailfinger
b23508f4cd Make the section checker executable.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@795 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-21 19:38:32 +00:00
Carl-Daniel Hailfinger
df65052e93 v3 does not handle .data* and .bss sections in stage1 and initram. We
simply hope they are unused/empty and will get runtime crashes/
corruption/malfunction if they are not empty. Same applies to any
sections with relocation entries which can not be resolved during
link time.

Check for the emptiness of these sections and abort the build on error.
This triggers on all stage1/initram global variables which are not
declared the right way. It also triggers on local static variables.

Features of this checker:
- It doesn't only check for non-empty .data and .bss, but also for
unknown sections which would be a problem.
- It gives you the offending filename, the section and the variable
  name.
- It won't stop after the first error and will tell you about all errors
for a given file list.

This found a long-standing bug introduced in r729 and fixed in r786.
It also broke the build of every Geode target in the v3 tree because
they had multiple bugs. And it broke the build of the K8 code because
of a bug there.
Other fixes resulting from this checker are in r790 and r791.

Ron already fixed some of the bugs uncovered by this checker.

Tested for all possible variations of .data and .bss usage.

Sample output follows:
  CC      build/coreboot.initram (XIP)
  CHECK   initram (non-empty writable/allocatable sections)
build/coreboot.initram_partiallylinked.o: section .data: foo1
build/coreboot.initram_partiallylinked.o: section .bss: foo2
build/coreboot.initram_partiallylinked.o: section .data.rel.ro.local:
msrnames.2746
make: *** [build/coreboot.initram] Error 1

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Segher Boessenkool <segher@kernel.crashing.org> 


git-svn-id: svn://coreboot.org/repository/coreboot-v3@794 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-21 17:43:04 +00:00
Ronald G. Minnich
4bb450cfa3 Emergency patch so that section checker won't bounce option tables.
Also gets rid of hard-codes in fwrite for strings that might, in future,
vary.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@791 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-21 15:49:29 +00:00
Ward Vandewege
bb12df9732 Fix typo in comment:
s/addrees/address/

Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@777 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-16 13:27:05 +00:00
Carl-Daniel Hailfinger
48fe3ab5ef Current v3 code has a big problem: Shared functions.
Calling non-PIC code from PIC code needs an ABI wrapper and we don't
provide one. Our trick with function pointers is exceedingly fragile:
- it depends on gcc not being clever enough
- it forces us to compile all initram source files in one go
- parallelizing initram compilation breaks the code
- compiling one initram source file at a time breaks the code
- enabling higher optimizations breaks the code
- enabling -fwhole-program breaks the code
- declaring the function pointers const breaks the code
- it's an undocumented side effect of gcc which will go away
- we need excessively ugly shared function wrappers
- the shared function wrappers had more than their fair share of bugs
- almost nobody understands the wrappers completely
- Segher warns against them: "So why do you think this should work?
You're telling it to link PIC to non-PIC. Did you read the manual? It's
just not allowed. It cannot ever work."

Kill the SHARED wrappers and use a real ABI wrapper.
The wrapper code is autogenerated on demand.
Any function compiled into stage0 is now shared by default, yet the size
and code generation of stage0/1/2 code are unchanged. Initram code size
does decrease quite a bit and the difficulty of creating shared
functions is now zero.

The patch includes extensive documentation about the inner workings of
the new wrappers and the reasons why they look like this.

Build and boot tested on qemu.
Build tested on all targets.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Ron says:
Wow. we've need this fix for a long time.

Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@775 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-16 00:10:25 +00:00
Ronald G. Minnich
8f064580dc Emergency commit as I have broken this tool.
Basically, anything that includes files from include/ should define 
STANDALONE, so that the includes don't try to created SHARED symbols. 

This was not a problem until we made get_option SHARED. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@755 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-13 03:07:21 +00:00
Ronald G. Minnich
dbdfc77314 Add support for dtc files that end in .dtc, e.g. ide.dtc.
This is managed by stripping the .dtc from the name when it
is used to label the node in the tree.
This one's for you Peter!

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@740 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-11 16:05:53 +00:00
Carl-Daniel Hailfinger
77010a1111 The named unions in the device tree code are obnoxious and degrade
readability. Move to anonymous unions.

Build tested on all targets. Boot tested on qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Ron tested this and it boots to Linux.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@730 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-10 00:20:24 +00:00
Ronald G. Minnich
2f5d7b66a9 1. fix dtc to properly put @x,y in hex, not decimal.
2. Fix trivial bug in dtc -- ioport is 6 chars long, not 3
3. Fix all dts so that the @ parts are now in hex.
4. fix graphics mem in dbs62 to be 16 MB, per artec.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@700 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-30 15:08:25 +00:00
Carl-Daniel Hailfinger
b1596f216b Rename mainboard_part_number to mainboard_name in various places. This
is the logical continuation of r416 which happened a year ago.

As an added bonus, we now have consistent naming again, making grepping
the source for dts properties possible.

Build tested on all targets. Patch attached for Gmail users.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@697 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-20 21:05:25 +00:00
Carl-Daniel Hailfinger
a4b90bacf4 Makes mainboard-vendor naming more consistent.
mainboard-name naming has been postponed because it's not clear what the
real name should be.

Generated code is identical to the state before the patch.
Compile tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@694 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-11 12:33:46 +00:00
Carl-Daniel Hailfinger
d9e875537b Move default mainboard vendor/subsystem from Kconfig to dts.
Compile tested including boundary cases.
Runtime tested on dbe62 by Ron. Works fine.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@693 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-09 21:21:39 +00:00
Patrick Georgi
ae2520e4bd Order libraries last on the command line when
building kconfig and lxdialog, so that their
content is used to resolve unknown symbols even
when they are static libraries.

Also fix HOST_LOADLIBS typo.

Signed-Off-By: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@690 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-06-06 20:47:42 +00:00
Mart Raudsepp
58a87f61c3 doxy: Fix doxygen build by renaming Doxyfile file from .LinuxBIOS to .coreboot, as the reference in build system was already changed to Doxyfile.coreboot back in January 27th
This makes doxygen documentation building work again.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@683 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-22 15:52:33 +00:00
Ronald G. Minnich
573d88e61d The Geode has MSRs. LOTS of MSR. I get confused trying to find them.
This program was originally written for OLPC and GX, and dumps all LX
registers used in coreboot. 
I have preserved the indent structure since that gives some idea of the
scope of variables. 
Of particular interest are the GLD variables, since they are always
listed as offsets in the manuals, 
and computing the actual number (for use in rdmsr etc.) can be really
tricky. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@681 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-09 16:12:41 +00:00
Ward Vandewege
e9f7d1de66 Fix code warning - val.type is a char, and NULL is not.
Thanks to Carl-Daniel for spotting this one, and Segher for providing the solution right away.

This is a trivial patch.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@667 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-26 12:05:08 +00:00
Ward Vandewege
a53508b751 Add generic array support to the coreboot dts output code.
This is necessary for the 'unwanted_vpci' field on geode-based boards.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@661 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-17 16:13:58 +00:00
Myles Watson
c4a9590044 This very short patch fixes nrv2b compression in lar.
It also fixes lzma compression in lar to fix the silent memory
corruption that was possible when files didn't compress well.

It adds some comments to both files and the file that calls them.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@658 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-04-14 14:19:09 +00:00