2. Fix trivial bug in dtc -- ioport is 6 chars long, not 3
3. Fix all dts so that the @ parts are now in hex.
4. fix graphics mem in dbs62 to be 16 MB, per artec.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@700 f3766cd6-281f-0410-b1cd-43a5c92072e9
is the logical continuation of r416 which happened a year ago.
As an added bonus, we now have consistent naming again, making grepping
the source for dts properties possible.
Build tested on all targets. Patch attached for Gmail users.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@697 f3766cd6-281f-0410-b1cd-43a5c92072e9
mainboard-name naming has been postponed because it's not clear what the
real name should be.
Generated code is identical to the state before the patch.
Compile tested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@694 f3766cd6-281f-0410-b1cd-43a5c92072e9
have a superio.
With this patch, alix1c and MFGPT work fine. Still need to test on Alix2c3, but it
is likely it will work.
Thanks to Marc and Jordan for this one.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@682 f3766cd6-281f-0410-b1cd-43a5c92072e9
in the pci dtc instead of the correct location in the domain.
Also fixed up some warnings on the const gliutable.
Tested on alix1c and boots to Linux, ethernet works. Still trying
to light up the display :-)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@617 f3766cd6-281f-0410-b1cd-43a5c92072e9
Note: You MUST have the later AMD VSA code that does not call bios
interrupts. If you use the older code, your boot will hang at this
point:
buf[0x20] signature is b0:10:e6:80
Call real_mode_switch_call_vsm
With post code 10
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@616 f3766cd6-281f-0410-b1cd-43a5c92072e9
the new settings as close as possible to the old settings.
All GeodeLX-based boards now include the geodelx/domain, geodelx/apic
and geodelx/pci dts files.
Remove "enabled" keyword from the alix.1c main dts. (That's the only
possibly critical change because it affects a working target. Tests on
hardware appreciated. Should be harmless, though.)
Compile tested only for msm800sev, norwich and dbe61, and the situation
is better than without the patch.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Tested and boots a working linux on alix1c.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@607 f3766cd6-281f-0410-b1cd-43a5c92072e9
code boots and works on qemu and
alix1c. It represents a huge change and a huge improvement. There are a
few fixes left to do, which
will come once this is in.
This change started out easy: get the device IDs OUT of the the dts, and
into one place. We
decided the device IDs should be in the constructors ONLY. To make a
long story short, that just did
not work out, and it revealed a flaw in the design. The result?
- no more ids in the various dts files.
- the constructor struct is gone -- one less struct, nobody liked the
name anyway
- the device_operations struct now includes the device id.
- constructor property no longer used; use device_operations instead.
- lpc replaced with ioport
All the changes below stem from this "simple" change.
I am finding this new structure much easier to work with. I hope we're
done
on this for real, however!
TODO:
1. Change limitation in dtc that makes it hard to use hex in pci@
notation.
Now for the bad news. Sometime today, interrupts or io or something
stopped working between r596 and r602 -- but I did no commits at
that point. So something has gone wrong, but I don't think it's this
stuff.
I did try a build of HEAD, and it fails really, really badly. Much
more badly than this fails, so I think this commit is only going
to improve things. It does work fine on qemu, fails on alix1c,
so I suspect one of today's "clean up commits" broke something.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@603 f3766cd6-281f-0410-b1cd-43a5c92072e9
from v2 to install them. Linux boots fine and all interrupts
seem to work correctly -- the network comes up, USB hot plug works,
I can mount the USB disk, etc.
To enable pirq tables for a given mainboard, simply add the
select PIRQ_TABLE (see below) to the Kconfig for that board.
Again, this code builds and boots linux on the alix1c.
I think, with this change, we are very close to moving ALL LX boards to
v3 and deprecating v2. The major remaining fix is to add an empty LAR
entry to fill empty space in LAR and speed up the LAR file search
process.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Index: include/tables.h
Add prototype, conditioned on CONFIG_PIRQ_TABLE
Index: util/x86emu/vm86.c
Comment out 'debug trap' code that scribbles vectors at 0x4000.
I don't know why this is here, but I'd like to leave it #if'ed out --
somebody, at some point, thought we needed it. To reenable, we will need
to move stage2 code or these magic vectors.
Index: arch/x86/Makefile
Add support for conditional compilation of pirq support code.
Index: arch/x86/pirq_routing.c
Add this file from v2.
Index: arch/x86/archtables.c
Add call to write_pirq_routing_table (controlled by #ifdef
CONFIG_PIRQ_TABLE)
Index: arch/x86/Kconfig
Add new config variable: PIRQ_TABLE
Index: device/device.c
Fix some trivial bugs.
Index: mainboard/pcengines/alix1c/Makefile
Add pirq table code for stage2
Index: mainboard/pcengines/alix1c/dts
Modify dts to properly set southbridge variables
Index: mainboard/pcengines/alix1c/irq_tables.c
Add code from v2 for the alix1c.
Index: mainboard/pcengines/Kconfig
Add 'select PIRQ_TABLE'
Index: include/arch/x86/pirq_routing.h
Add include file from v2.
Remove all the SLOTCOUNT nonsense. This hack was only needed
for a very early version of gcc 3.x, where they screwed up the
creation of struct members that used the [] syntax for variable-length
array at the end of the struct.
Index: include/device/pci.h
Add prototype
git-svn-id: svn://coreboot.org/repository/coreboot-v3@582 f3766cd6-281f-0410-b1cd-43a5c92072e9
Press <Enter> for default boot, or <Esc> for boot prompt...
boot: hda1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200
malloc_diag: alloc: 240 bytes (3 blocks), free: 16136 bytes (1 blocks)
malloc_diag: alloc: 256 bytes (4 blocks), free: 16120 bytes (1 blocks)
file_open: dev=hda1, path=/vmlinuz
ide_probe: ide_probe drive #0
ide_probe: ctrl 1188096 base 0
find_ide_controller: found PCI IDE controller 1022:209a prog_if=0x80
find_ide_controller: primary channel: compatibility mode
find_ide_controller: cmd_base=0x1f0 ctrl_base=0x3f4
Sadly, it locks up at this point, but this is still progress.
I realize the location of the defines is a little odd, but I think it is useful to have
them right next to the function that uses them.
Index: southbridge/amd/cs5536/cs5536.c
cs5536.c: add ide support functions from v2
Index: mainboard/pcengines/alix1c/dts
Correct error in southbridge pcipath. Add enable_ide to dts.
Index: southbridge/amd/cs5536/dts
Add dts for enable_ide.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@575 f3766cd6-281f-0410-b1cd-43a5c92072e9
released new-model VSA code.
Changes:
Index: util/dtc/flattree.c
Add an ID entry for apic properties.
Index: northbridge/amd/geodelx/apic
This is a new dts for the northbridge used as an APIC.
Index: northbridge/amd/geodelx/pci
This is a new dts for the northbridge used as a PCI device.
Index: northbridge/amd/geodelx/geodelx.c
Fix a non-obvious bug: we had set phase3 scan bus for both the
domain AND the PCI device, which is a mistake: can't scan from the
PCI device too.
Index: northbridge/amd/geodelx/domain
This is a new dts for the northbridge used as an pci domain.
Created via svn move dts domain
Index: device/pci_device.c
If there are leftover devices, it is now a warning, not an error,
since there are
some no-pci devices in the tree now. For future: only complain about
leftover PCI devices ...
Index: device/device.c
make devcnt a global and initialize it in init_dev. Add a debug printk.
Index: mainboard/pcengines/alix1c/dts
Add an 'apic' entry for the mainboard. This actually looks pretty clean
to me, the way it went in.
Index: northbridge/amd/geodelx/vsmsetup.c
Delete all pcibios int support, no longer needed for VSA.
Please note that this patch includes Carl-Daniel's improvements
below, which I have Ack-ed.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
A few minor comments. It would be great if you could address them before
committing.
northbridge/amd/geodelx/domain is a copy of northbridge/amd/geodelx/dts.
You probably want to use "svn mv" for that because it preserves history
and the old file was probably intended to have been moved, not copied.
northbridge/amd/geodelx/vsmsetup.c:247: warning: ‘biosint’ defined but
not used
Since the new VSA does not use BIOSINT services anymore, deleting
biosint and related functions from vsmsetup.c would shrink vsmsetup.c by
one fourth. Patch follows (could you merge it into your patch?):
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@571 f3766cd6-281f-0410-b1cd-43a5c92072e9
- I left LB_TAG_ intact because they are used by the payloads
- file renames are still missing. see next commit
- some lb_ renames might be missing. feel free to provide patches.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@564 f3766cd6-281f-0410-b1cd-43a5c92072e9
northbridge has several constructors, so it is required, if these
constructors
are to be compiled in to the running image, that a dts be provided.
To use the dts, one must add a /config/ line to the components
that use it, hence the change to the mainboard dts .
This change does not produce a working bios as far as I can tell.
But it is still important to have it in.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@555 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@525 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@521 f3766cd6-281f-0410-b1cd-43a5c92072e9
