from v2 to install them. Linux boots fine and all interrupts
seem to work correctly -- the network comes up, USB hot plug works,
I can mount the USB disk, etc.
To enable pirq tables for a given mainboard, simply add the
select PIRQ_TABLE (see below) to the Kconfig for that board.
Again, this code builds and boots linux on the alix1c.
I think, with this change, we are very close to moving ALL LX boards to
v3 and deprecating v2. The major remaining fix is to add an empty LAR
entry to fill empty space in LAR and speed up the LAR file search
process.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Index: include/tables.h
Add prototype, conditioned on CONFIG_PIRQ_TABLE
Index: util/x86emu/vm86.c
Comment out 'debug trap' code that scribbles vectors at 0x4000.
I don't know why this is here, but I'd like to leave it #if'ed out --
somebody, at some point, thought we needed it. To reenable, we will need
to move stage2 code or these magic vectors.
Index: arch/x86/Makefile
Add support for conditional compilation of pirq support code.
Index: arch/x86/pirq_routing.c
Add this file from v2.
Index: arch/x86/archtables.c
Add call to write_pirq_routing_table (controlled by #ifdef
CONFIG_PIRQ_TABLE)
Index: arch/x86/Kconfig
Add new config variable: PIRQ_TABLE
Index: device/device.c
Fix some trivial bugs.
Index: mainboard/pcengines/alix1c/Makefile
Add pirq table code for stage2
Index: mainboard/pcengines/alix1c/dts
Modify dts to properly set southbridge variables
Index: mainboard/pcengines/alix1c/irq_tables.c
Add code from v2 for the alix1c.
Index: mainboard/pcengines/Kconfig
Add 'select PIRQ_TABLE'
Index: include/arch/x86/pirq_routing.h
Add include file from v2.
Remove all the SLOTCOUNT nonsense. This hack was only needed
for a very early version of gcc 3.x, where they screwed up the
creation of struct members that used the [] syntax for variable-length
array at the end of the struct.
Index: include/device/pci.h
Add prototype
git-svn-id: svn://coreboot.org/repository/coreboot-v3@582 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@581 f3766cd6-281f-0410-b1cd-43a5c92072e9
This is not terribly clean but it works.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Tested with a qemu boot to work correctly.
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@580 f3766cd6-281f-0410-b1cd-43a5c92072e9
them just use the default.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@579 f3766cd6-281f-0410-b1cd-43a5c92072e9
to a board should add a defconfig in mainboard/vendor/board/defconfig.
I think that the defconfig should:
1. Use the ROM size that comes with the board
2. Enable compression
3. Not include a payload
This will make it easy for buildrom or anyone who wants to build it
manually to use lar to add their payloads. It also allows buildrom to
keep the configs in the coreboot tree.
The patch also adds mainboard/emulation/qemu-x86/defconfig
Signed-off-by: Myles Watson <myles@pel.cs.byu.edu>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@578 f3766cd6-281f-0410-b1cd-43a5c92072e9
the .constructor struct member.
This error is so subtle that we might consider changing the device code; or at least
working on the documentation to make it more clear. The key question: do we ever want
an operations struct that can NOT operate as a device constructor? When this code was
designed over a year ago, it seemed that we might; now, it is not so certain.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@577 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@576 f3766cd6-281f-0410-b1cd-43a5c92072e9
Press <Enter> for default boot, or <Esc> for boot prompt...
boot: hda1:/vmlinuz root=/dev/hda1 console=tty0 console=ttyS0,115200
malloc_diag: alloc: 240 bytes (3 blocks), free: 16136 bytes (1 blocks)
malloc_diag: alloc: 256 bytes (4 blocks), free: 16120 bytes (1 blocks)
file_open: dev=hda1, path=/vmlinuz
ide_probe: ide_probe drive #0
ide_probe: ctrl 1188096 base 0
find_ide_controller: found PCI IDE controller 1022:209a prog_if=0x80
find_ide_controller: primary channel: compatibility mode
find_ide_controller: cmd_base=0x1f0 ctrl_base=0x3f4
Sadly, it locks up at this point, but this is still progress.
I realize the location of the defines is a little odd, but I think it is useful to have
them right next to the function that uses them.
Index: southbridge/amd/cs5536/cs5536.c
cs5536.c: add ide support functions from v2
Index: mainboard/pcengines/alix1c/dts
Correct error in southbridge pcipath. Add enable_ide to dts.
Index: southbridge/amd/cs5536/dts
Add dts for enable_ide.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@575 f3766cd6-281f-0410-b1cd-43a5c92072e9
Due to some problems with PCI transactions, Geode LX needs the ROM cache properties to be write-serialize + cache disabled by runtime. More details below.
Add mainboard_pre_payload() call to each mainboard as the final coreboot function before the payload is called by stage1.
Note that this patch also grows the bootblock from 16K to 20K to make room for mainboard_pre_payload().
"The problem is a transaction depth issue and bottlenecks inside the GX
and LX that go across PCI. The conditions are very complicated but it
comes down to we need write serialization for writes to PCI. If you
look in the data book you can't have write serialization and the cache
enabled on a given area. During coreboot we don't have to worry about
a write or a PCI bus master so I think we can enable caching the ROM.
After coreboot we can't be sure what will happen in the system so we
need to set it up to be safe. For example flashrom just clears the
write protect bit. If the cache were enabled (no write serialization)
and flashrom was writing the ROM we would be in a precarious position.
A PCI bus master doing a read or a write that has a hit on a tag
would cause enough bottleneck conditions that it might hit the bug. We
could change flashrom but that doesn't help other tools. We need to
leave the system in a safe state. Also, caching the ROM after it is no
longer used doesn't make much sense. So, we need a call just before
the payload runs to clean up the system."
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@573 f3766cd6-281f-0410-b1cd-43a5c92072e9
turn gets cache turned on much sooner. The system boots a bit faster.
We're still far too slow, perhaps because we are not caching ROM?
Index: arch/x86/Makefile
Add ../../northbridge/amd/geodelx/geodelxinit.o object
Index: arch/x86/geodelx/geodelxinit.c
add sizeram function.
Index: arch/x86/geodelx/stage1.c
add called to northbridge_init_early()
Index: northbridge/amd/geodelx/Makefile
remove geodelxinit.o object
Index: northbridge/amd/geodelx/geodelx.c
remove call to northbridge_init_early()
remove sizeram function.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@572 f3766cd6-281f-0410-b1cd-43a5c92072e9
released new-model VSA code.
Changes:
Index: util/dtc/flattree.c
Add an ID entry for apic properties.
Index: northbridge/amd/geodelx/apic
This is a new dts for the northbridge used as an APIC.
Index: northbridge/amd/geodelx/pci
This is a new dts for the northbridge used as a PCI device.
Index: northbridge/amd/geodelx/geodelx.c
Fix a non-obvious bug: we had set phase3 scan bus for both the
domain AND the PCI device, which is a mistake: can't scan from the
PCI device too.
Index: northbridge/amd/geodelx/domain
This is a new dts for the northbridge used as an pci domain.
Created via svn move dts domain
Index: device/pci_device.c
If there are leftover devices, it is now a warning, not an error,
since there are
some no-pci devices in the tree now. For future: only complain about
leftover PCI devices ...
Index: device/device.c
make devcnt a global and initialize it in init_dev. Add a debug printk.
Index: mainboard/pcengines/alix1c/dts
Add an 'apic' entry for the mainboard. This actually looks pretty clean
to me, the way it went in.
Index: northbridge/amd/geodelx/vsmsetup.c
Delete all pcibios int support, no longer needed for VSA.
Please note that this patch includes Carl-Daniel's improvements
below, which I have Ack-ed.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
A few minor comments. It would be great if you could address them before
committing.
northbridge/amd/geodelx/domain is a copy of northbridge/amd/geodelx/dts.
You probably want to use "svn mv" for that because it preserves history
and the old file was probably intended to have been moved, not copied.
northbridge/amd/geodelx/vsmsetup.c:247: warning: ‘biosint’ defined but
not used
Since the new VSA does not use BIOSINT services anymore, deleting
biosint and related functions from vsmsetup.c would shrink vsmsetup.c by
one fourth. Patch follows (could you merge it into your patch?):
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@571 f3766cd6-281f-0410-b1cd-43a5c92072e9
emulation.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@570 f3766cd6-281f-0410-b1cd-43a5c92072e9
Clean up lib.h prototypes.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@568 f3766cd6-281f-0410-b1cd-43a5c92072e9
Fix spd_read_byte prototype.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@567 f3766cd6-281f-0410-b1cd-43a5c92072e9
/config/ = "northbridge/amd/geodelx";
Then the file northbridge/amd/geodelx/dts is read in and processed.
Magic(TM) appends the name "/dts" to the path.
This hack is fine with chips that only do one thing.
But some (all) northbridge parts play several roles: APIC cluster, PCI domain
device, and PCI device. The result is a need for more than one dts, since
there are three possible devices, with three types of IDs, and so on.
To keep things sane, I am proposing to enable multiple dts files in a
directory, names (e.g., nothing required here):
domaindts
pcidts
apicdts
(of course these names can be anything, this is just an example).
This change will require a change to the dtc, since we can no longer
assume just one dts file, and hence need a way to name these different
files.
The proposed change is very simple. We now require the full path name
for the file, and eliminate the Magic(TM).
So,
/config/ = "northbridge/amd/geodelx/pcidts";
will open the pcidts file.
/config/ = "northbridge/amd/geodelx/domaindts";
will open the domain dts.
Maybe we should just call it domain and pci and apic? works for me.
/config/ = "northbridge/amd/geodelx/domain";
/config/ = "northbridge/amd/geodelx/pcibridge";
/config/ = "northbridge/amd/geodelx/apic";
Changes:
dtc.c: create a new function, fopenfile, that will only open a path if it
really is a file. Modify dtc_open_file to use this function. fopenfile
assumes "-" means stdin; should it, or should I move that assumption back
to dtc_open_file?
dtc.h: add prototypes
dtc-parser.y: Given a config path, open the path.
southbridge/amd/cs5536/cs5536.c: example of how C code changes
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Please see the comments below, but they do not have to be addressed for
this commit, just keep them in mind for future commits in that area.
git-svn-id: svn://coreboot.org/repository/coreboot-v3@566 f3766cd6-281f-0410-b1cd-43a5c92072e9
- I left LB_TAG_ intact because they are used by the payloads
- file renames are still missing. see next commit
- some lb_ renames might be missing. feel free to provide patches.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@564 f3766cd6-281f-0410-b1cd-43a5c92072e9
cosmetic comment as well.
We just did lots of coding work to make sure we could call vsmbios.
So let's actually call it!
P.S. If this is NOT considered a cosmetic comment, feel free to yell at
me :-)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@563 f3766cd6-281f-0410-b1cd-43a5c92072e9
.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@562 f3766cd6-281f-0410-b1cd-43a5c92072e9
is running the VSA in the geode lx northbridge.
It builds but is not tested.
lar.h: make LAR functions SHARED
lar.c: make process_file non-static (i.e. global)
vsmsetup.c: modify to use LAR functions.
stage1.c: new function, init_archive, which is SHARED and will set up
the initial archive struct.
Note that some work remains. The use of unsigned longs and unsigned
shorts should be changed to u32/u16 as Carl-Daniel has pointed out,
Because this change requires changes elsewhere I am not including them
in this patch.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@561 f3766cd6-281f-0410-b1cd-43a5c92072e9
done, long term,
is to remove almost all of the vsmsetup.c file and use functions in the
vm86.c file.
The barrier to achieving that goal is the specialized nature of the vga
bios support code vs. the vsm bios support code.
There are a few issues to resolve but what I'd like
to do is get VSA working first, then work out how to merge the rest of
the code.
I have already done some merging at this point.
This code does not yet work. But the board does not work either, and I
want to get the code into the repo in case my hard drive dies.
Makefile: add vmsetup.o
vsmsetup.c: Add this file from v2. Fix copyright and includes.
Remove almost all assembly code in favor of code in vm86.c.
In future, almost all code will be removed and the vm86.c code used
instead.
vm86.c: make some assembly symbols .globl so that vsmsetup.c can use
them.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@560 f3766cd6-281f-0410-b1cd-43a5c92072e9
Remove old vendor,device struct members since we are now using the
device_id struct.
Change declaration of dev_find_device to use device_id struct.
device/device_util.c
Change dev_find_device to use device_id struct instead of vendor, device
parameters.
Add convenience function, dev_find_pci_device, to make it easier for
users.
device/pci_device.c
Change uses of dev->vendor and dev->device to dev->id.
Change prints of dev->vendor, dev->device to use the
dev_id_string function.
device/pci_rom.c
Change uses of dev->vendor and dev->device to dev->id.
southbridge/amd/cs5536/cs5536.c
Change uses of dev_find_device to dev_find_pci_device
southbridge/amd/cs5536/dts
Add pciid of the cs5536
northbridge/amd/geodelx/dts
add pciid of the geodelx northbridge.
util/x86emu/vm86.c
Change uses of dev_find_device to dev_find_pci_device
With these changes, the chipsetinit function now finds the southbridge
in the static tree, which is the first time this has worked in v3.
This success in turn means that the chipsetinit code is running for the
first time.
We are still failing in "Finding PCI configuration type"
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@558 f3766cd6-281f-0410-b1cd-43a5c92072e9
Change the ID constants so they are more useful for debugging.
Instead of simple 1,2,3 they now are a 4-byte value which can be more
useful when looking at memory with a debugger. Lots of variables can be
'1', but fewer variables will match to 'PCID'.
include/device/pci.h:
Include pci_ids.h in pci.h
device/device.c: remove silly comment. Change memcpy to struct assign, this makes it possible
for the C compiler to do type checking. Add assign for the dev->id.
flattree.c: Support the use of 'domainid' and 'pciid' in the per-chip dts. These IDs will be assigned
to the static tree device struct. In conjunction with the earlier patch, this change removes the need
for users to assign the ops struct member in the dts by hand, as it is done in the qemu port today.
The ops struct member will automatically be assigned by the dev_init function, which is run
in stage2 before any actual device code is run. (This change to dev_init was in the previous patch).
Added two comments that document what is going on.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@557 f3766cd6-281f-0410-b1cd-43a5c92072e9
I just uncovered this problem while trying to get the lx going.
The symptom was that the northbridge ops were never getting run,
in particular the phase 2 ops for the geodelx were not running. The
reason was that the ops struct member for the device was not set.
How is the ops struct member set?
Currently, the ops vector for a static device (i.e. a device created from the
dts) has to be set by hand, as in mainboard/emulation/qemu-x86/dts:
domain0 {
/config/("northbridge/intel/i440bxemulation");
ops = "i440bxemulation_pcidomainops";
This requirement is ridiculous (it's my fault). If we know the part,
and have the dts, we should not have to explicitly name the ops. In fact the
constructors array, defined at the end of the various device files, makes
searching for an ops struct for a dynamic device automatic. We should
support this automatic behavior for static devices too.
Given the function find_constructor
in device/device.c, why don't we just use that? The problem is that we did
not set up the device struct to include a device id, just a device path, and
find_constructor requires a device_id -- which makes sense, I hope,
as the path is its pci path (e.g. 0:1.0) and the constructors are defined by the
device id (i.e. it is the same constructor for a given part, no matter how many
of the part we have).
So, as a start to fixing this limitation (this is going to take several patches),
I've done the following:
1. add a struct device_id to the device struct.
2. extended the dev_init code in device/device.c -- this is the first function
called from lib/stage2.c -- to find a constructor for the dev->id and, if
found, set dev->ops to it.
Result: for static devices with the id set, the ops pointer will be set
automatically. Coreboot builds fine with this change.
The next change will be to add dtc commands to set ids.
Currently, we have commands like pcipath, pcidomain, etc.;
the new commands will look like pciid, domainid, etc. Once we have these
commands, we will have made it possible to set ops automatically. We
can just set the ids in the device dts file, and users will never have to
see any of this complication.
The final change will be a bit more complicated. Right now, if you look in,
e.g., northbridge/amd/geodelx/dts, you'll see that we have one dts, but
the northbridge plays three roles. We can't easily contain those three
roles in one dts (I am open to suggestions showing I am wrong).
I am going to propose that we have more than one dts file
in a directory, so instead of
northbridge/amd/geodelx/dts
we would have
northbridge/amd/geodelx/dtsdomain
northbridge/amd/geodelx/dtsapic
northbridge/amd/geodelx/dtspci
so that we could set the variables for each of these individual components.
There is no need to split geodelx.c into three .c files, however.
Finally, I will be removing the archaic vendor and device unsigned's from
the device struct in future, but as I say, I am trying to stage these changes
to keep them understandable.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@556 f3766cd6-281f-0410-b1cd-43a5c92072e9
northbridge has several constructors, so it is required, if these
constructors
are to be compiled in to the running image, that a dts be provided.
To use the dts, one must add a /config/ line to the components
that use it, hence the change to the mainboard dts .
This change does not produce a working bios as far as I can tell.
But it is still important to have it in.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@555 f3766cd6-281f-0410-b1cd-43a5c92072e9
processor. However, nothing in the log tells the user why the processor
is being reset.
Example log follows:
LinuxBIOS-3.0.0 Fri Jan 11 15:53:52 MST 2008 starting...
Choosing fallback boot.
[...]
Fallback failed. Try normal boot
LAR: Attempting to open 'normal/initram/segment0'.
[...]
LAR: CHECK normal/initram/segment0 @ 0xfffc49b0
start 0xfffc4a00 len 5564 reallen 5564 compression 0 entry 0x000010ca
loadaddress 0x00000000
Entry point is 0xfffc5aca
pll_reset: read msr 0x4c000014
_MSR GLCP_SYS_RSTPLL (4c000014) value is: 00000398:0000181e
Configuring PLL
LinuxBIOS-3.0.0 Fri Jan 11 15:53:52 MST 2008 starting...
Choosing fallback boot.
[...]
Print an informative message before resetting the processor.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@553 f3766cd6-281f-0410-b1cd-43a5c92072e9
make: *** No rule to make target `LinuxBIOSv3/build/stage0-prefixed.o',
needed by `LinuxBIOSv3/build/linuxbios.initram'.
Stop.
Signed-off-by: Robert Millan <rmh@aybabtu.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@552 f3766cd6-281f-0410-b1cd-43a5c92072e9
generic x86 code. For the old supported CAR sizes, the newly generated
code is equivalent, so it should be a no-brainer.
The patch is identical (except one build fix) to what was committed in
r3038 to v2.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@551 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@550 f3766cd6-281f-0410-b1cd-43a5c92072e9
numeric constants and #defines for such constants. Since grepping the
tree shouldn't be necessary to find a POST code and we already have
too many duplicated POST codes, gather almost all of them in a common
header file.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@549 f3766cd6-281f-0410-b1cd-43a5c92072e9
return from disable_car.
- Move the cache as ram memory to 0x80000 instead of 0xc8000, as the C
range is really tricky to get right :-)
- Modify the geode disable_car to ensure the cache is flushed to ram on
the wbinvd.
With these changes, I get a payload loaded.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@546 f3766cd6-281f-0410-b1cd-43a5c92072e9
use it.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@544 f3766cd6-281f-0410-b1cd-43a5c92072e9
available to C.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@543 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@542 f3766cd6-281f-0410-b1cd-43a5c92072e9
any object already mentioned in STAGE0_OBJ.
This saves 386 bytes in qemu stage2 (~240 bytes after LZMA compression).
Build tested and runtime tested in Qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@540 f3766cd6-281f-0410-b1cd-43a5c92072e9
The message appears if a file has not been found in the LAR archive and
is triggered even by lookup routines. Normal capitalization helps
reducing the frightening effect of the message.
Correct a few typos in other areas of the LAR code as well.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@538 f3766cd6-281f-0410-b1cd-43a5c92072e9
_MAINOBJECT #defined. Calls from all other files ended up in nirvana
because the compiler was not able to calculate the address of the
wrapper for the absolute call. The linker tried, but failed miserably.
Use the -combine flag and compile all of initram at once. This enables
GCC to calculate the address of the abscall wrapper, resulting in
working code.
Segher Boessenkool thinks the patched code works only by accident
because GCC has no way to specify generation of XIP code. According to
him, future GCC versions or other circumstances may break the code.
While this patch makes code work for now, it does NOT check whether the
generated code tries to write to memory outside the stack (general
writable data). That will of course fail, but I hope porters are smart
enough to avoid that.
Corey Osgood writes:
Great work tracking this down! This is okay for now, but we need to look
for a better solution in the future. Counting on porters who may or may
not remember this discussion to avoid something isn't good
future-proofing.
Checking the ELF sections for read-write data and stopping the build
with an error could make this future-proof.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@537 f3766cd6-281f-0410-b1cd-43a5c92072e9
may be due to miscompilation of XIP objects which do not have
_MAINBOBJECT defined. This issue was impossible to see on qemu because
no such object existed. Introduce initram_printktest.c in the Qemu
target, which will test for miscompilation and crash with a descriptive
error message.
This has been build tested and runtime tested on Qemu, and with my
compiler/linker combination it indeed crashes.
gcc (GCC) 4.2.1 (SUSE Linux)
GNU ld (GNU Binutils) 2.17.50.20070726-14 (SUSE Linux)
Trying with gcc-4.1 (GCC) 4.1.3 20070724 (prerelease) (SUSE Linux) and
the linker above had exactly the same results.
Unless we manage to fix the bug uncovered by this patch, leaving the
Qemu target in crashing state is the best thing we can do because this
behaviour mirrors the state of all other targets.
Ron says: I am comfortable with this. If hardware is broken, qemu should
be broken. I avidly wait the fix :-)
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@535 f3766cd6-281f-0410-b1cd-43a5c92072e9
into lib/northbridgelib.c.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@534 f3766cd6-281f-0410-b1cd-43a5c92072e9
across all of these makefiles. The rules are now in order of execution
during boot, that is:
STAGE0_MAINBOARD_OBJ
INITRAM_OBJ
STAGE2_MAINBOARD_OBJ
As added benefit, mainboard makefiles are now almost identical.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@533 f3766cd6-281f-0410-b1cd-43a5c92072e9
