Commit graph

1179 commits

Author SHA1 Message Date
Ronald G. Minnich
649c9f99ff Console:
(1)we now compile in all printks, which is good: we can print any message provided we can change
the console log level at any time. 
(2) The console log level is compiled in and unchangeable, which is bad, as it defeats the purpose of (1).

Add a BIOS_ALWAYS log level. Make console log level a variable. Make functions that set it and get it
visible everywhere. Always print out the version message; this is really *not* noise!

PCI: Simplify pci functions so that they can be used in stage1 or anywhere for that matter. Add
a find function which is needed for many stage1 functions. Note that we copy but also clean up
the libpayload stuff just a bit. 

Get rid of config space type 2. If there was ever a platform that used it, I don't know what it was, 
and the presence is a needless distraction. 

tested and working on DBE62 (which means the console and the pci functions work :-).

There is a remaining problem with dumplxmsrs which nobody understands. It prints out garbage if we use the 
%s for the msr names. 

Formatting is an issue; if somebody wants to fix formatting they can assume I will ack it. Sorry, 
my emacs has gone just nuts. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@729 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-09 21:03:57 +00:00
Ronald G. Minnich
df4565d288 Fix some typos.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@728 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-09 20:23:56 +00:00
Carl-Daniel Hailfinger
71d814fac6 Change the GAS bug workaround in CAR code to be more readable.
The problem was that gas treated whitespace asargument delimiter.
Removing the whitespace in crtitical places is the most obvious fix.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@727 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-09 19:16:43 +00:00
Carl-Daniel Hailfinger
22fe1e55c3 Fix the following build error:
OPTIONS build/mainboard/gigabyte/m57sli/option_table.c
Error - Range end (122) does not match define (125) in line
checksum 392 983 984

cmos.layout did not conform to the requirements of the option table
creation code.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@726 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-09 15:59:17 +00:00
Carl-Daniel Hailfinger
3436faee69 Remove Family 10h revision Ax support from v3 CAR code. This is an
errata for early silicon and is not mentioned in the public rev guide.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@725 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-09 13:45:22 +00:00
Ronald G. Minnich
3b31e382a9 SMBUS support for mcp55 and v3.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@724 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-06 23:31:35 +00:00
Ronald G. Minnich
5aabbccc93 trivial forgot to add it
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@723 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-05 02:59:00 +00:00
Ronald G. Minnich
da9286b479 State of the tree for K8
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@722 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-05 02:48:54 +00:00
Ronald G. Minnich
8ad705f72c Self-acking fix of a stupid typo.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@721 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-05 01:24:38 +00:00
Ronald G. Minnich
54b7a9609f With a bug fix from peter and a suggest change by Carl-Daniel
Resource map and a way to use the pci config stuff from stage 1, done in 
a way that will work in stage 2 (but only for systems that use type 1
config cycles; will fail for type MEM config cycles). 

We need to rethink the PCI config stuff per Stepan's comment, in part 
because the device tree now includes things that are NOT PCI devices. 
Stepan's suggestion, to make the functions take busdevfn as the 
parameter, makes a lot of sense. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.s


git-svn-id: svn://coreboot.org/repository/coreboot-v3@720 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-05 01:19:37 +00:00
Ronald G. Minnich
24d5ad5466 Trivial fix: fix include name for macros.h
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@719 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-04 00:39:28 +00:00
Ronald G. Minnich
84c313733d Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@718 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-03 23:36:44 +00:00
Ronald G. Minnich
30c0db46ed We're getting closer. It has been pointed out that this code is not pretty. I agree. Get
it working, then we'll get it pretty. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@717 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-03 22:42:01 +00:00
Ronald G. Minnich
c945259136 Closer to compiling. Will be bringing in the rest of the functions for this part today.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@716 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-03 19:39:35 +00:00
Ronald G. Minnich
58b7d6b482 This mostly compiles.
Also, per Uwe, remove the \r\n for \n

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@715 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-03 19:36:53 +00:00
Carl-Daniel Hailfinger
1a09707fd6 Convert stage2 and initram makefile rules from object to source files.
This creates a clearer distinction between source files in the source 
tree we want to have compiled and indirectly created object/source files 
in the object tree.

It also will make enable us to move to whole-program 
optimization/compilation which should yield substantial size savings.
Then again, we may be able to do that without the makefile conversion as 
well.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@714 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-02 20:56:11 +00:00
Peter Stuge
41242a63c3 v3: k8/m57sli wip1
This is not nearly complete, but just the current state of my tree.

k8/raminit.c does not compile at all. Lots of fixes are still needed to bring
it working into v3. I've gone through about 1/8 of the file, it errors out on
line 576 now.

The mcp55 files are in a very early state and also do not compile for me, so
I've disabled them by commenting out the select in mainboard/gigabyte/Kconfig.

Once northbridge/amd/k8/raminit.c builds, k8_ops needs to be added, then we
may actually see the first v3 k8 build. :)

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@713 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-02 03:34:05 +00:00
Peter Stuge
2a74b39793 v3: Port ITE IT8716F superio code from v2
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@712 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-02 03:29:02 +00:00
Peter Stuge
bc131a77de v3: More amdk8 -> amd/k8 fixups
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@711 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-02 01:45:04 +00:00
Peter Stuge
1564bcac15 v3: Remove compiler warning about unused variable by only declaring when used
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@710 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-02 01:44:27 +00:00
Peter Stuge
1b1d130d92 v3: Fix up amd_k8.h -> amd/k8/k8.h includes after the previous svn mv
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@709 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-01 23:19:05 +00:00
Carl-Daniel Hailfinger
aaea9aacab The Geode LX RAMinit code already has textual register names in the
debug routine. Use them for printout.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@708 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-01 19:39:13 +00:00
Carl-Daniel Hailfinger
56a909a52e Fix up the Gigabyte M57SLI target to conform to the new style
introduced in r605.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@707 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-01 18:03:18 +00:00
Ronald G. Minnich
526a61a6e5 rename per IRC
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@706 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-01 18:00:54 +00:00
Carl-Daniel Hailfinger
03dca375db Right now, our Kconfig files in the mainboard/ directory in the v3 tree
are not exactly in the best shape.
- MAINBOARD_NAME is claimed to be the mainboard name, but it is used 
  exclusively as mainboard directory.
- MAINBOARD_NAME is set in mainboard/$VENDOR/$BOARD/Kconfig to
  $VENDOR/$BOARD, but mainboard/$VENDOR/Kconfig already hardcodes
  $VENDOR/$BOARD as board path.
- MAINBOARD_NAME has a help text which will never be displayed to
  the user.

The diffstat is encouraging: A total of 200 lines have been
removed completely.

Per-board Kconfig files have been deleted, the remnants making sense
have been merged into per-vendor Kconfig files and the never-shown help
texts have been removed.

If there are ever some real per-board options and not just tricks to
make the makefiles behave, we can resurrect the per-board Kconfig files.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@705 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-01 17:40:22 +00:00
Ronald G. Minnich
ea5e263466 move amdk8 to amd/k8 per IRC discussion
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@704 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-01 17:26:06 +00:00
Ronald G. Minnich
178f27bc31 v3: Clean up a Kconfig value and fixup K8 CAR defines to get CONFIG_ values
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@703 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-01 17:16:45 +00:00
Ronald G. Minnich
06ced7c09a The m57sli almost builds. It's pretty empty. The dtc is not run .
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@702 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-01 17:03:22 +00:00
Ronald G. Minnich
935c99a3a9 minor include stuff.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>

Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@701 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-01 16:59:09 +00:00
Ronald G. Minnich
2f5d7b66a9 1. fix dtc to properly put @x,y in hex, not decimal.
2. Fix trivial bug in dtc -- ioport is 6 chars long, not 3
3. Fix all dts so that the @ parts are now in hex.
4. fix graphics mem in dbs62 to be 16 MB, per artec.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@700 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-30 15:08:25 +00:00
Ronald G. Minnich
96914e1655 1. geodelx.c: cover case of unterminated DRAM by adding a terminated
parameter to two functions. 
2. geodelx.h: define DRAM_TERMINATED and DRAM_UNTERMINATED constants
3. dbe62/initram.c: move to auto PLL control, so set MANUALCONF to 0
4. all other initram.c: set up calls to cpu_reg_init with proper 
   TERMINATED/UNTERMINATED constants. 

builds for dbe62. The auto PLL strapping is tested and works. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@699 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-29 15:54:46 +00:00
Ronald G. Minnich
bc75f3349d Add names for control bits.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>



Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@698 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-25 19:44:08 +00:00
Carl-Daniel Hailfinger
b1596f216b Rename mainboard_part_number to mainboard_name in various places. This
is the logical continuation of r416 which happened a year ago.

As an added bonus, we now have consistent naming again, making grepping
the source for dts properties possible.

Build tested on all targets. Patch attached for Gmail users.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@697 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-20 21:05:25 +00:00
Marc Jones
33654d8321 There was a programming error which made most USB port4 setup wrong. This
patch uses byte pointer and the MMIO read and write functions. 

Signed-off-by: Marc Jones <marc.jones@amd.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@696 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-14 23:04:48 +00:00
Uwe Hermann
72d1721ea1 Fix a build-error for the ADL MSM800SEV.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@695 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-12 12:03:55 +00:00
Carl-Daniel Hailfinger
a4b90bacf4 Makes mainboard-vendor naming more consistent.
mainboard-name naming has been postponed because it's not clear what the
real name should be.

Generated code is identical to the state before the patch.
Compile tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@694 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-11 12:33:46 +00:00
Carl-Daniel Hailfinger
d9e875537b Move default mainboard vendor/subsystem from Kconfig to dts.
Compile tested including boundary cases.
Runtime tested on dbe62 by Ron. Works fine.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@693 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-09 21:21:39 +00:00
Carl-Daniel Hailfinger
0f05bd42db - Clean up Geode companion chip CS5536 code.
- Eliminate a few redundant dev_find_pci_device() calls.
- Fix a compile warning intruduced in r689.

This should be an equivalence transformation.

Build tested on norwich, db800, alix.1c, alix.2c3, dbe62, dbe61.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@692 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-07-03 19:42:05 +00:00
Patrick Georgi
ef90e728ab Implements console and serial lbtable records compatible to cbv2 as of r3396
Signed-Off-By: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@691 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-06-29 06:43:01 +00:00
Patrick Georgi
ae2520e4bd Order libraries last on the command line when
building kconfig and lxdialog, so that their
content is used to resolve unknown symbols even
when they are static libraries.

Also fix HOST_LOADLIBS typo.

Signed-Off-By: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@690 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-06-06 20:47:42 +00:00
Ronald G. Minnich
e1ef6d2dc8 This change adds some debug prints, and a comment warning to dts on cs5536.
Most importantly it fixes a simple programming error which made it so most of
the sets on the USB were not doing anything. The bug is also in V2.

With this fix, the DBE62 USB ports all work!

If someone clones the fix to V2, it will also fix V2. Or, we can just convince
you to move forward to V3 :-)

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@689 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-06-04 14:36:35 +00:00
Ronald G. Minnich
dba27d1bcd This patch gets usb port 3 on dbe62 working and sets up a dts-based way to map
USB EHCI power control registers to power enables pins 1 and 2. 

Why doesn't port 4 work? Who knows. That's a problem for another day. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>


Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@688 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-06-03 15:22:16 +00:00
Mart Raudsepp
11490d2898 artecgroup/dbe61: Set up 4MB mode for LPC dongle
This way we can fit a kernel and initramfs on the dongle's free ~3.75MB space
and have a debug system bootable right from inside the dongle. The start
address of the dongle is mem@0xffc00000 for FILO with 4MB minus ROM area
available.

This should be a no-op when not booting from the dongle.

The same change was done to artecgroup/dbe62/stage1.c in rev660.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@687 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-28 01:00:36 +00:00
Mart Raudsepp
c26b7ea48e artecgroup/dbe61: Set up some video memory, as the device has VGA output.
This allows me to have a working coreinfo payload on DBE61 with coreboot-v3.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@686 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-28 00:58:59 +00:00
Carl-Daniel Hailfinger
9700b1e3b6 Fix a typo in r684 which caused compilation to fail. Trivial.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@685 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-23 19:59:43 +00:00
Carl-Daniel Hailfinger
6198dc8271 Print current and wanted LZMA scratchpad size in the decompression
routine. That allows people to either adjust compression parameters
or scratchpad size.
Having a similar check during build time would be nice.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@684 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-23 19:56:50 +00:00
Mart Raudsepp
58a87f61c3 doxy: Fix doxygen build by renaming Doxyfile file from .LinuxBIOS to .coreboot, as the reference in build system was already changed to Doxyfile.coreboot back in January 27th
This makes doxygen documentation building work again.

Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@683 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-22 15:52:33 +00:00
Ronald G. Minnich
dc231a7041 This is the fix for MFGPT on those boards which have a cs5536 and ALSO
have a superio.
With this patch, alix1c and MFGPT work fine. Still need to test on Alix2c3, but it
is likely it will work.

Thanks to Marc and Jordan for this one.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@682 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-09 21:48:28 +00:00
Ronald G. Minnich
573d88e61d The Geode has MSRs. LOTS of MSR. I get confused trying to find them.
This program was originally written for OLPC and GX, and dumps all LX
registers used in coreboot. 
I have preserved the indent structure since that gives some idea of the
scope of variables. 
Of particular interest are the GLD variables, since they are always
listed as offsets in the manuals, 
and computing the actual number (for use in rdmsr etc.) can be really
tricky. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@681 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-09 16:12:41 +00:00
Ward Vandewege
e31836b6af This puts USB and eth2 on IRQ 11 (eth1 was already on IRQ 11). This makes the
kernel much happier.

As Marc suggested, having these devices all on the same IRQ seems to be fine.
I've tested performance - I get 11MB/sec copying data from eth2 to eth1, as
well as from eth2 to eth0 (which is on a different IRQ). That's 90% of
wirespeed which is what I'd expect to see.

Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@680 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-05-09 14:00:57 +00:00