hardware and have a specific size.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1069 f3766cd6-281f-0410-b1cd-43a5c92072e9
pci_set_resources. There is no matching pci_bus_set_resources, so it's
confusing to see the dev function in the bus structures.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1048 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@955 f3766cd6-281f-0410-b1cd-43a5c92072e9
cleanups/fixes.
Fixup device tree code. Add/change methods as needed.
This should help serengeti.
Signed-off-by: Ronald G. Minnich<rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@954 f3766cd6-281f-0410-b1cd-43a5c92072e9
size indicated by byte 31 of SPD.
Memory is still not working; hanging in dqs training.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@854 f3766cd6-281f-0410-b1cd-43a5c92072e9
next step is to fix up this:
LAR build/coreboot.rom
Bootblock coreboot.bootblock does not appear to be a bootblock.
Error adding the bootblock to the LAR.
make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error
1
make: exit 2
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@809 f3766cd6-281f-0410-b1cd-43a5c92072e9
image, and fails:
LAR build/coreboot.rom
Bootblock coreboot.bootblock does not appear to be a bootblock.
Error adding the bootblock to the LAR.
make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error
1
Next step is to get rid of all warnings that are not #warning.
Then it is on to simnow.
Anyone who wants to work on the warnings is most welcome to.
DBE62 still builds with no problems.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@808 f3766cd6-281f-0410-b1cd-43a5c92072e9
Rename files and functions as needed.
There is regularity to the naming. Stage1 stuff is called stage1_*. The rest is not.
Most .c files have a corresponding .dts. The code is simpler and smaller and has less
duplication.
Most (all) romcc artifacts removed.
I've made a lot of effort to get copyright headers done correctly, using 'svn log'.
next are the 8132, 8151, and serengeti, then comes simnow.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@767 f3766cd6-281f-0410-b1cd-43a5c92072e9
