mirror of
https://github.com/fail0verflow/switch-coreboot.git
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f28a44eb48
image, and fails: LAR build/coreboot.rom Bootblock coreboot.bootblock does not appear to be a bootblock. Error adding the bootblock to the LAR. make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error 1 Next step is to get rid of all warnings that are not #warning. Then it is on to simnow. Anyone who wants to work on the warnings is most welcome to. DBE62 still builds with no problems. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@808 f3766cd6-281f-0410-b1cd-43a5c92072e9
241 lines
6.4 KiB
C
241 lines
6.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2003 Linux NetworX
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console.h>
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#include <device/device.h>
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/pci.h>
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#include <msr.h>
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#include <legacy.h>
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#include <device/pci_ids.h>
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#include <statictree.h>
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#include <config.h>
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#include <device/smbus.h>
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#include <mc146818rtc.h>
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#include "amd8111.h"
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#include "amd8111_smbus.h"
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#define PREVIOUS_POWER_STATE 0x43
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#define MAINBOARD_POWER_OFF 0
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#define MAINBOARD_POWER_ON 1
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#define SLOW_CPU_OFF 0
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#define SLOW_CPU__ON 1
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#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL
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#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
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#endif
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static int lsmbus_recv_byte(struct device * dev)
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{
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int do_smbus_recv_byte(u16 smbus_io_base, u16 device);
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unsigned device;
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struct resource *res;
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device = dev->path.i2c.device;
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res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
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return do_smbus_recv_byte(res->base, device);
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}
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static int lsmbus_send_byte(struct device * dev, u8 val)
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{
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int do_smbus_send_byte(u16 smbus_io_base, u8 device, u8 val);
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unsigned device;
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struct resource *res;
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device = dev->path.i2c.device;
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res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
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return do_smbus_send_byte(res->base, device, val);
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}
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static int lsmbus_read_byte(struct device * dev, u8 address)
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{
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int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address);
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unsigned device;
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struct resource *res;
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device = dev->path.i2c.device;
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res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
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return do_smbus_read_byte(res->base, device, address);
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}
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static int lsmbus_write_byte(struct device * dev, u8 address, u8 val)
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{
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int do_smbus_write_byte(u16 smbus_io_base, u8 device, u8 address, u8 val);
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unsigned device;
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struct resource *res;
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device = dev->path.i2c.device;
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res = find_resource(get_pbus_smbus(dev)->dev, 0x58);
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return do_smbus_write_byte(res->base, device, address, val);
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}
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#ifdef CONFIG_ACPI_TABLE
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unsigned pm_base;
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#endif
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static void acpi_init(struct device *dev)
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{
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u8 byte;
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u16 word;
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u16 pm10_bar;
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u32 dword;
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int on;
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#if 0
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printk(BIOS_DEBUG, "ACPI: disabling NMI watchdog.. ");
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byte = pci_read_config8(dev, 0x49);
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pci_write_config8(dev, 0x49, byte | (1<<2));
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byte = pci_read_config8(dev, 0x41);
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pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<2));
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/* added from sourceforge */
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byte = pci_read_config8(dev, 0x48);
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pci_write_config8(dev, 0x48, byte | (1<<3));
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printk(BIOS_DEBUG, "done.\n");
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printk(BIOS_DEBUG, "ACPI: Routing IRQ 12 to PS2 port.. ");
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word = pci_read_config16(dev, 0x46);
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pci_write_config16(dev, 0x46, word | (1<<9));
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printk(BIOS_DEBUG, "done.\n");
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#endif
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/* To enable the register 0xcf9 in the IO space
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* bit [D5] is set in the amd8111 configuration register.
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* The config. reg. is devBx41. Register 0xcf9 allows
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* hard reset capability to the system. For the ACPI
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* reset.reg values in fadt.c to work this register
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* must be enabled.
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*/
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byte = pci_read_config8(dev, 0x41);
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pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5));
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/* power on after power fail */
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on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
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get_option(&on, "power_on_after_fail");
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byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
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byte &= ~0x40;
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if (!on) {
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byte |= 0x40;
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}
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pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
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printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
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/* switch serial irq logic from quiet mode to continuous
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* mode for Winbond W83627HF Rev. 17
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*/
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byte = pci_read_config8(dev, 0x4a);
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pci_write_config8(dev, 0x4a, byte | (1<<6));
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/* Throttle the CPU speed down for testing */
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on = SLOW_CPU_OFF;
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get_option(&on, "slow_cpu");
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if(on) {
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pm10_bar = (pci_read_config16(dev, 0x58)&0xff00);
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outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
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dword = inl(pm10_bar + 0x10);
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on = 8-on;
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printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
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(on*12)+(on>>1),(on&1)*5);
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}
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#ifdef CONFIG_ACPI_TABLE
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pm_base = pci_read_config16(dev, 0x58) & 0xff00;
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printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base);
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#endif
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}
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static void acpi_read_resources(struct device * dev)
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{
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struct resource *resource;
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/* Handle the generic bars */
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pci_dev_read_resources(dev);
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/* Add the ACPI/SMBUS bar */
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resource = new_resource(dev, 0x58);
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resource->base = 0;
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resource->size = 256;
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resource->align = log2(256);
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resource->gran = log2(256);
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resource->limit = 65536;
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resource->flags = IORESOURCE_IO;
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resource->index = 0x58;
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}
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static void acpi_enable_resources(struct device * dev)
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{
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u8 byte;
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/* Enable the generic pci resources */
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pci_dev_enable_resources(dev);
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/* Enable the ACPI/SMBUS Bar */
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byte = pci_read_config8(dev, 0x41);
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byte |= (1 << 7);
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pci_write_config8(dev, 0x41, byte);
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/* Set the class code */
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pci_write_config32(dev, 0x60, 0x06800000);
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}
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static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device)
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{
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pci_write_config32(dev, 0x7c,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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static struct smbus_bus_operations lops_smbus_bus = {
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.recv_byte = lsmbus_recv_byte,
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.send_byte = lsmbus_send_byte,
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.read_byte = lsmbus_read_byte,
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.write_byte = lsmbus_write_byte,
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};
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static struct pci_operations lops_pci = {
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.set_subsystem = lpci_set_subsystem,
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};
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struct device_operations acpi = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_8111_ACPI}}},
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.constructor = default_device_constructor,
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.phase3_scan = scan_static_bus,
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.phase4_enable_disable = amd8111_enable,
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.phase4_read_resources = acpi_read_resources,
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.phase4_set_resources = pci_dev_set_resources,
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.phase5_enable_resources = acpi_enable_resources,
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.phase6_init = acpi_init,
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.ops_pci = &lops_pci,
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.ops_smbus_bus = &lops_smbus_bus,
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};
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