Commit graph

145 commits

Author SHA1 Message Date
Stefan Reinauer
1a5f05b02c rename VM86 to REALMODE in v3, too, as that is what it really is.
(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1171 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-06-07 17:36:43 +00:00
Pattrick Hueper
6258e1e826 add YABEL flag to options to decide wether access to devices other than the one yabel is running for is possible
Signed-off-by: Pattrick Hueper <phueper@hueper.net>
Tested and Acked-by: Joseph Smith <joe@settoplinux.org>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1154 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-03-18 16:26:56 +00:00
Pattrick Hueper
f8b3fed317 add YABEL Debug Flag config variable
Signed-off-by: Pattrick Hueper <phueper@hueper.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1148 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-03-14 15:43:25 +00:00
Ronald G. Minnich
5a90884bd4 last kontron commit.
This is a potentially good pointer to where someone can take this. 

While startup was working, BSP now explodes once the AP stops, while
BSP is doing startup IPI loop send #2. The code needs to be hardened; I 
think use of the shared variables would really make it much more solid. 
This would be a good undergrad student project if someone is looking for one.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1145 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-03-11 16:17:37 +00:00
Myles Watson
cc295dd73a This patch removes all *_PLUGIN_SUPPORT options and replaces most
*_SUPPORT options with NO_*_SUPPORT options.  This means that you have
to specify that you want a smaller BIOS, otherwise you get full
functionality.

HyperTransport is the only exception for a couple of reasons.  HT
requires a mainboard.h file which not all mainboards have, and it's
less likely to be "plugged in" to a board that doesn't have some
onboard HT.

It also fixes a trivial typo in Kconfig (paylaod -> payload)

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1140 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-25 17:50:38 +00:00
Myles Watson
9d6d811dd1 This patch converts __FUNCTION__ to __func__, since __func__ is standard.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1131 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-12 21:15:34 +00:00
Myles Watson
502c22bf13 Move Plugin menu and make it depend on experimental.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1126 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-02-09 22:25:59 +00:00
Myles Watson
7f6b02dcb1 This patch adds the domain's resources and all links to the tree traversal for
constraining resources.  Build and boot tested on qemu, serengeti, and
alix2c3.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1112 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-01-09 14:17:06 +00:00
Mart Raudsepp
2d5920e5ba Remove unused pciconf.h header with constants that everyone uses by value instead per convention
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1110 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-01-08 17:21:37 +00:00
Myles Watson
403cb4754c This patch implements preorder traversal for Phase 2 and Phase 6, and prints a
warning that Phase 1 is obsolete if anyone implements one.

The only difference between the Phase 2 and Phase 6 implementations is that
phase2_fixup is always called if it's defined, but phase6_init is only called if
the device is enabled.

Note that any devices not found in the tree will not have their init functions
called with this patch.  I think that's a good thing, but it will require some
dts fixes.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1108 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-01-08 16:19:51 +00:00
Myles Watson
d2f540f35e This patch introduces {PCIX,PCIE,AGP...}_SUPPORT config variables.
Kconfig:
       Add *_SUPPORT variables.
       Add select statements for the hardware that needs them.

device/Makefile:
       Test *_SUPPORT variables instead of chip names.

device/Kconfig:
       Add *_PLUGIN_SUPPORT variables.

device/pci_device.c:
       Conditionally include headers if *_PLUGIN_SUPPORT.
       Update default drivers to depend on CONFIG_*_PLUGIN_SUPPORT.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1097 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-01-05 22:57:45 +00:00
Myles Watson
7d47daf0a8 This trivial patch makes AGP support compile again.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1095 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-01-05 17:41:55 +00:00
Myles Watson
bdc76a22a0 This patch fixes up k8 for the new resource allocator. It splits
northbridge functions and makes devices children of the northbridge.
	
northbridge/amd/k8/domain.c: 
	Add the functions from k8/pci.c that belong to the domain.  Add
support for physical link numbers in resource indices.  Combine find_iopair
and find_mempair to find_regpair.

northbridge/amd/k8/pci.c:
	Remove functions that went to the domain.

device/hypertransport.c:
	Add support for HT connections from devices that aren't the bus
controller.

device/hypertransport.h:
	Change the prototype of hypertransport_scan_chain.

northbridge/amd/k8/pci:
	Take out bridge flag.

mainboard/amd/serengeti/stage1.c
	Change first register usage.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1094 f3766cd6-281f-0410-b1cd-43a5c92072e9
2009-01-05 16:00:32 +00:00
Myles Watson
0fb2a8f081 This patch simplifies the resource allocator by splitting it into distinct
phases.  One benefit of this is that it makes the call chain easier to follow.

device/device.c:
	Remove references to have_resources.
	Remove read_resources from compute allocate resources.
	Split compute_allocate_resources into two
	1. compute_resource_needs
		A. Traverse the tree depth first
		B. Sum resources
		C. Adjust limits and bases
		D. Update bridge resources sizes
	2. assign_resource_values
		A. Traverse the tree breadth first
		B. Assign resource values

device/device_util.c:
	Remove references to have_resources.

device/pci_device.c:
	Remove saved values stubs (they're not needed now.)
		1. Sizing function restores values
	Fix 64-bit flag masking.
	Add an error message for an invalid value.
	Update pci_record_bridge_resource:
		1. remove compute_allocate_resource call
		2. remove pci_set_resource call
	Update pci_bus_read_resources to read children's too.
	Update pci_set_resource:
		1. change logic for setting zero-size resources
			A. Set range to [limit->limit-2^gran]
				(Could have been any range with base > limit)
		2. remove compute_allocate_resource calls
		3. Change phase4_assign_resources ->phase4_set_resources

device/pci_ops.c:
	Change an error message to be more helpful.

device/root_device.c:
	Remove code for read_resources and set resources.
	Add a .id to the ops.

include/device/device.h:
	Remove have_resources.
	Comment out assign_resources.  I think we could comment out more here.
	Add debugging function prototypes.
	Change phase4_assign_resources to phase4_set_resources.

include/device/resource.h
	Add a IORESOURCE_BRIDGE flag.

device/cardbus_device.c
	Remove compute_allocate_resource call.
	Use probe_resource (doesn't die) instead of find_resource.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1089 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-31 19:43:34 +00:00
Myles Watson
80aa586a51 Subject: [PATCH 4/5] integration of biosemu (aka YABEL) into coreboot
Signed-off-by: Pattrick Hueper <phueper@hueper.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1076 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-16 22:46:55 +00:00
Myles Watson
695d74985e This patch cleans up a little whitespace and makes the ID mismatch error more
verbose in pci_rom.c.  Suggested by Pattrick on the list.  Trivial.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1072 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-16 18:32:01 +00:00
Myles Watson
539a101e1b This patch changes unsigned [int] to u16 for subsystem IDs. They're in the
hardware and have a specific size.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1069 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-10 19:07:16 +00:00
Myles Watson
7c14a50c1c This patch makes all the SuperIOs build again, and reverts some breakage that
I introduced earlier.

It adds a placeholder in the fintek SuperIO so the array indexing works.
It moves the enable to make the struct more compatible with v2.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1066 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-12-08 20:40:02 +00:00
Myles Watson
72c2e85313 This patch changes all occurrences of pci_dev_set_resources ->
pci_set_resources.  There is no matching pci_bus_set_resources, so it's
confusing to see the dev function in the bus structures.
 
Signed-off-by: Myles Watson <mylesgw@gmail.com>

Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://coreboot.org/repository/coreboot-v3@1048 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-24 14:06:10 +00:00
Myles Watson
12a3094274 This patch makes subsystem ids work. Here are the changes by file:
device/pci_device.c:
    Only update IDs if:
    - The device is on the mainboard
    - The device has a Vendor ID and Device ID
    - The device has a set_subsystem function in ops_pci(dev)

util/dtc/flattree.c:
    Make devices from the dts be on_mainboard.
    If they're plugged in, they shouldn't be in the dts.

mainboard/amd/serengeti/dts:
    Add subsystem_vendor and subsystem_device.

Build tested on Serengeti.  Getting closer :)

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1045 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-19 03:05:33 +00:00
Uwe Hermann
09f70836fd This is the first part of a v3 Super I/O refactoring.
Add a small collection of PNP enter/exit functions for many Super I/Os.
Use these functions instead of duplicating them for each chip.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1044 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-18 22:32:05 +00:00
Myles Watson
d1eeba86f0 This patch clarifies/fixes some debug output.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1039 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-17 19:18:36 +00:00
Myles Watson
27fbb8428c This patch changes PNP support for devices so that the dts values get passed
in.

include/device/pnp.h:
	Add enable, val, and irq & drq structs.

superio/winbond/w83627hf/superio.c:
	Change functions to operate on children.
	Add device ID to ops.
	Add enables to pnp_dev_info table.
	Fill in dts values.

superio/winbond/w83627hf/dts:
	Get rid of device number parameters.
	Add config parameters so we know when they're set.

device/pnp_device.c:
	Allocate devices as children to SuperIO.

mainboard/amd/serengeti/dts:
	Move ioport so it's found. (Not its permanent resting place I hope.)
	Add enables for KBC, SP1, and HWM to show it off.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1027 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-14 21:45:10 +00:00
Myles Watson
981c3652a1 This patch adds some debug functions, cleans up whitespace (per indent), and adds const in a few places.
include/device/path.h
	Make path_eq take const path*.
	
include/device/device.h
	Use const with dev_path, dev_id_string, bus_path, find_dev_path,
	andalloc_find.

device/device.c
	Add functions for tree printing of devs and resources.
	Change %p to more useful info.

device/device_util.c
	Use const changes from device.h.

lib/stage2.c
	Use updated printing functions.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@1024 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-14 16:15:33 +00:00
Myles Watson
f3e9e1dd35 This patch continues the device code cleanup.
The largest changes are to get_pci_bridge_ops, and related changes to make it
compile and use correct declarations.  

While I was doing that I moved the checks for CONFIG_<BUS>_PLUGIN_SUPPORT to
the Makefile.

The only functional difference is a possible NULL dereference in a debug
statement.

I also added a few more consts, now that my other patch is in.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@983 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-05 22:27:36 +00:00
Myles Watson
966cb29c69 This patch clarifies/adds comments and changes names in device/pci_device.c
It also changes %p debug statements in various places.  I think they get in
the way of diffs when you have log files to compare.  I don't want to see the
allocation differences most of the time.  I turned most of them into NULL
checks.  If they were supposed to be "Where are we in device allocation?"
checks, we could make them into that too.

It's a work-in-progress. Comments welcome.

I think most of the changes are self explanatory, but this one might not be:

If you are reading all the BARs from a device, and you come to a 64-bit BAR.
No matter why you skip it, you should skip it as a 64-bit BAR, and not try to
read the upper half as the next 32-bit BAR.

Because of that, set the 64-bit flag IORESOURCE_PCI64 early, and don't clear
it on return.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@980 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-11-04 21:32:59 +00:00
Myles Watson
7741b2273c This patch clarifies comments and changes a little whitespace in device/device.c
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@966 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-31 17:57:42 +00:00
Ronald G. Minnich
cfa4c50225 This is the beginning of support for saving base registers that already have a v
alue. There 
is a known bug in v2/v3 wherein a BAR that is set is ignored. This change will c
ome in very
slowly as it is a bit tricky to get right as we redesign the dev code.

Also make the vm86 stuff use the SRC instead of OBJ names so we can see it in ks
cope. 

Finally, beginnings of documentation changes, not finished yet. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@965 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-31 17:40:01 +00:00
Ronald G. Minnich
86a45fd25a Make it so that read_resources only reads resources.
dev_phase4 will call compute_allocate. This is an early pass at 
making the device tree code a little more readable. We have done a 
pass on the stage2 code and are comfortable with phases 1-3 and 5-6; 
phase 4 is the phase that is really tough to follow. We are working
on cleaning that up today. 

This change tested and working on dbe62. 

We are well aware that as more complex targets appear this code
may break on them. At the same time, we are determined to untangle the 
thicket of code in phase 4, since this code has been a source of 
confusion for several years now. 

There used to be a recursion: compute_allocate_resource would ALWAYS
call read_resources, which would in turn call compute_allocate_resource. 

We are attempting to resolve this in a clearer manner. 

boots to linux on dbe62
boots to etherboot on qemu

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@963 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-29 18:29:19 +00:00
Ronald G. Minnich
3eec9e7790 General cleanup and comments for things that should be fixed in future.
Most substantive change is getting rid of 'initialized', which was only
ever needed in v2 due to an implementation mistake.

With Uwe's comments taken into account, 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@961 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-29 04:25:32 +00:00
Myles Watson
12f47ecf89 This fixes the 8132 so that it can be included in the build for serengeti.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@956 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-28 02:06:15 +00:00
Ronald G. Minnich
cedf16ca69 Marc reviewed the v3 device tree code and we developed the set of
cleanups/fixes.

Fixup device tree code. Add/change methods as needed. 
This should help serengeti.
Signed-off-by: Ronald G. Minnich<rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Marc Jones <marc.jones@amd.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@954 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-27 20:05:38 +00:00
Uwe Hermann
9b90a6f22b Fix a bunch of Doxygen warnings in v3 (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@951 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-23 18:55:01 +00:00
Myles Watson
0bc9279b49 Because the enable bit was masked off, checking for 0xffffffff didn't work. This patch changes the place where the bit is masked. The other way to fix it would be to check for 0xfffffffe.
V2 doesn't seem to have the problem.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@926 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-14 12:27:23 +00:00
Uwe Hermann
8e6d45e059 Minor fixes and improvements for v3, mostly for Kconfig files (trivial).
- Coding style and whitespace fixes.
 - Remove obsolete comments, fix incorrect ones.
 - Use the full/canonical name of mainboards/vendors everywhere.
 - Update the list of USB Debug capable chipsets from
   http://www.coreboot.org/EHCI_Debug_Port.
 - s/LB/CB/ for the CONSOLE_PREFIX kconfig option.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@879 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-01 18:29:22 +00:00
Ronald G. Minnich
76167990ed Bringing the m57sli to life. This includes changes to mcp55 and
mainboard that we learned with the serengeti that we needed. New 
function in pnp that is for reading. new prototype in pnp.h. New 
constants for ite8716f. 

This board does not build yet; we are exercising code in k8 north that
the serengeti did not enable. More tomorrow. 

Now that we have two boards under way we can hopefully see our way to 
getting more put in. The 690 is the obvious next choice. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@876 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-10-01 06:47:51 +00:00
Ronald G. Minnich
28ecbeab88 The K8 is one example, but there are other devices (e.g. I2C) that also have
multiple links. The way this was done in v2 was a big confusing; this way is 
less so. 

The changes are easy. Getting them right has been hard :-)

First, for a k8 north that has three links, you can name each one as follows:
pci0@18,0
pci1@18,0
pci2@18,0

We have to have the same pcidevfn on these because that is how the k8 works. 
But the unit numbers (pci0, pci1, etc.) distinguish them. 

The dts will properly generate a "v3 device code" 
compatible static tree that puts the links in the right place in the 
data structure. 

The changes to dts are trivial. 
As before, dts nodes with children are understood to be a bridge. 
But what if there is a dts entry like this:
pci1@18,0 {/config/("northbridge/amd/k8/pci");};


This entry has no children in the dts. 
How does dt compiler know it is a bridge? It can not know unless 
we add information to the dts for that northbridge part. 
To ensure that all bridge devices are detected, we support the following: 
if a dts node for a device has a bridge property, e.g.: 
 {
        device_operations = "k8_ops";
       bridge;
 };

The dt compiler will treat it as a bridge whether it has children or not. 

Why would a device not have children? Because it might be attached to a
pci or other socket, and we don't know at build time if the socket is empty, 
or what might be in the socket. 

This code has been tested on dbe62 and k8 simnow, and works on each. 
It is minimal in size and it does what we need. I hope it resolves our 
discussion for now. We might want to improve or change the device code
later but, at this point, forward motion is important -- I'm on a deadline for
a very important demo Oct. 22!

Also included in this patch are new debug prints in k8 north. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@865 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-17 16:36:20 +00:00
Ronald G. Minnich
c24361eba7 remaining fixes for log2. Simple prototype added to spd_ddr2.h
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@853 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-31 20:39:48 +00:00
Carl-Daniel Hailfinger
a3dd66b628 Improve pci scan debugging. This helped me find a rather nasty bug.
Message level is BIOS_SPEW for everything except error conditions.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@845 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-29 09:06:13 +00:00
Stefan Reinauer
87adbc377b small dependency fix, plus make oldconfig & co need libintl, too :)
(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@842 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-28 22:44:49 +00:00
Ronald G. Minnich
62f8ea8e9b This set of changes gets us much farther, in fact, we get into initram.
This means that basic resource maps are working, initial hypertransport 
setup is working, the amd8111 ISA device is working, config space is 
working for all the parts, we can grow the FLASH part address space to 
more than 64k, and in general we're having a good time. 

Here is the output:
coreboot-3.0.824 Tue Aug 26 22:18:21 PDT 2008 starting... 
(console_loglevel=8)
Choosing fallback boot.
LAR: Attempting to open 'fallback/initram/segment0'.
LAR: Start 0xfff80000 len 0x80000
LAR: normal/option_table@0xfff80000, size 1776
LAR: normal/initram/segment0@0xfff80740, size 24404
LAR: normal/stage2/segment0@0xfff866f0, size 1
LAR: normal/stage2/segment1@0xfff86750, size 18542
LAR: normal/stage2/segment2@0xfff8b010, size 559
LAR: normal/payload/segment0@0xfff8b290, size 18142
LAR: bootblock@0xffff7fc0, size 32768
LAR: File not found!
LAR: Run file fallback/initram/segment0 failed: No such file.
Fallback failed. Try normal boot
LAR: Attempting to open 'normal/initram/segment0'.
LAR: Start 0xfff80000 len 0x80000
LAR: normal/option_table@0xfff80000, size 1776
LAR: normal/initram/segment0@0xfff80740, size 24404
LAR: CHECK normal/initram/segment0 @ 0xfff80740
start 0xfff80790 len 24404 reallen 24404 compression 0 entry 0x00000004 
loadaddress 0x00000000
Entry point is 0xfff80794
Hi there from stage1
stage1 returns
run_file returns with 0

Goal for tomorrow is to get initram done. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@826 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-27 05:30:50 +00:00
Ronald G. Minnich
081602b211 More sensible way to conditionally include hypertransport.c
Builds both K8 and Geode bioses with no trouble.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnch <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@811 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-24 06:16:03 +00:00
Ronald G. Minnich
159354e6ba If you get a warning, it's because you SHOULD be getting a warning.
next step is to fix up this:
   LAR     build/coreboot.rom
Bootblock coreboot.bootblock does not appear to be a bootblock.
Error adding the bootblock to the LAR.
make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error 
1
make: exit 2

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@809 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-24 03:27:28 +00:00
Ronald G. Minnich
f28a44eb48 This now compiles (with many warnings but ...) and tries to build a rom
image, and fails: 
  LAR     build/coreboot.rom
Bootblock coreboot.bootblock does not appear to be a bootblock.
Error adding the bootblock to the LAR.
make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error 
1

Next step is to get rid of all warnings that are not #warning. 

Then it is on to simnow. 

Anyone who wants to work on the warnings is most welcome to. 

DBE62 still builds with no problems. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@808 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-24 02:59:05 +00:00
Carl-Daniel Hailfinger
70c96e3919 Improve/fix PCI device doxygen comments.
Thanks to Ron for explaining this.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@801 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-22 11:10:04 +00:00
Ronald G. Minnich
44d1585458 per discussion w/AMD, remove all conditionals based on REV_F.
It's all REV_F now and we're wasting time pretending otherwise. This 
change simplifies the code and will continue to simplify the code. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@788 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-18 20:31:34 +00:00
Carl-Daniel Hailfinger
67accc1f69 Fix Kconfig dependencies and update defconfigs.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@784 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-18 16:48:27 +00:00
Carl-Daniel Hailfinger
94a2225b36 Factor out PCI subsystem ID setting. This cleans up the code as well,
arguably fixes some strange behaviour and prepares the code for
per-device subsystem ID setting.
It's the first step to achieve the per-device subsystem goal.

Boot tested on qemu.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@761 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-14 09:28:28 +00:00
Carl-Daniel Hailfinger
3cff5b912d The device code had several unclear messages, leading to
confusion when analyzing the logs. Improve readability.

This code may be obsolete, but that's not entriely sure yet.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@759 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-14 01:40:31 +00:00
Ronald G. Minnich
99792d89fc Emergency patch for an ancient bug in device_util.c, self-acked:
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: : Ronald G. Minnich <rminnich@gmail.com>
smbus_ops patched
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@758 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-14 00:02:27 +00:00