It requires a flag (CONFIG_SCAN_BUILD) to be set, and then
$ scan-build make
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1146 f3766cd6-281f-0410-b1cd-43a5c92072e9
*_SUPPORT options with NO_*_SUPPORT options. This means that you have
to specify that you want a smaller BIOS, otherwise you get full
functionality.
HyperTransport is the only exception for a couple of reasons. HT
requires a mainboard.h file which not all mainboards have, and it's
less likely to be "plugged in" to a board that doesn't have some
onboard HT.
It also fixes a trivial typo in Kconfig (paylaod -> payload)
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1140 f3766cd6-281f-0410-b1cd-43a5c92072e9
The reset value for NAND timings is the slowest possible for Flash interface.
Implement optionally setting it to a different value inside the NAND device.
Set it to appropriate values for Artec Group DBE61 and DBE62.
This results in a roughly two times quicker read time as measured by hdparm
for these boards.
Because we can not cast to southbridge_amd_cs5536_nand_config if the board dts
does not have an entry for the NAND device, this change proposes a method for
reasonably clean way to only optionally compile in support for certain devices:
If a board wants to support an optional device, its Kconfig entry can select
that configuration. If it's optional even across the same board, it can expose
a subconfig option of the board, that describes it and if chosen selects the
device config. The source code for that device is conditionally compiled only
if the Kconfig option gets enabled by the configuration for the board.
A requirement is that if the board configuration can enable a device, it is
contained in the boards dts file as well.
A perhaps better long-term alternative for this could be making dtc generate
preprocessor definitions for each device_configuration struct that it creates.
Then the source code file is always enabled, but that file can be wrapped
around a simple #ifdef check in its entirety.
Conversion to the alternative approach from the short-term Kconfig approach
proposed here should be relatively easy, as to not block inclusion of the
Kconfig approach in the short term.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1138 f3766cd6-281f-0410-b1cd-43a5c92072e9
Peter has some valid points that need to be addressed in the future. See his
Ack message.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1100 f3766cd6-281f-0410-b1cd-43a5c92072e9
Kconfig:
Add *_SUPPORT variables.
Add select statements for the hardware that needs them.
device/Makefile:
Test *_SUPPORT variables instead of chip names.
device/Kconfig:
Add *_PLUGIN_SUPPORT variables.
device/pci_device.c:
Conditionally include headers if *_PLUGIN_SUPPORT.
Update default drivers to depend on CONFIG_*_PLUGIN_SUPPORT.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1097 f3766cd6-281f-0410-b1cd-43a5c92072e9
a user/developer to disable the option table, so it doesn't overwrite whatever
the factory BIOS has written. Also fix building with OPTION_TABLE disabled.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1078 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@998 f3766cd6-281f-0410-b1cd-43a5c92072e9
This actually starts to get compile errors, instead of config errors.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@994 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@993 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@971 f3766cd6-281f-0410-b1cd-43a5c92072e9
current v2 support, but rather an older version I was working on that used too
many registers. It will be ported to v2 (eventually).
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@930 f3766cd6-281f-0410-b1cd-43a5c92072e9
dbe62 was tested and works i.e. this does no harm.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@894 f3766cd6-281f-0410-b1cd-43a5c92072e9
- Coding style and whitespace fixes.
- Remove obsolete comments, fix incorrect ones.
- Use the full/canonical name of mainboards/vendors everywhere.
- Update the list of USB Debug capable chipsets from
http://www.coreboot.org/EHCI_Debug_Port.
- s/LB/CB/ for the CONSOLE_PREFIX kconfig option.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@879 f3766cd6-281f-0410-b1cd-43a5c92072e9
chosen via Kconfig. Default off.
Depending on the target, this saves between 10% and 20% of initram size.
Compilation still broken for:
- ADL MSM800SEV
- Gigabyte M57SLI
Compilation changed for:
- AMD DB800 (checker doesn't trigger anymore, but we get an unresolved
symbol instead)
- AMD Norwich (same)
(The compilation changes are not bad per se, just a bit misleading. It
seems that gcc 4.2.x is really smart. gcc 4.3.x and later are even
smarter and even fix compilation completely.)
Compilation OK for:
- AMD Serengeti
- Artec DBE61
- Artec DBE62
- PCEngines Alix.1C
- PCEngines Alix.2C3
-
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@825 f3766cd6-281f-0410-b1cd-43a5c92072e9
image, and fails:
LAR build/coreboot.rom
Bootblock coreboot.bootblock does not appear to be a bootblock.
Error adding the bootblock to the LAR.
make: *** [/home/rminnich/src/bios/coreboot-v3/build/coreboot.rom] Error
1
Next step is to get rid of all warnings that are not #warning.
Then it is on to simnow.
Anyone who wants to work on the warnings is most welcome to.
DBE62 still builds with no problems.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@808 f3766cd6-281f-0410-b1cd-43a5c92072e9
it. Since it was the only content of the i440bxemulation northbridge
Kconfig, kill that file as well.
The i440BX RAM size is determined from the dts and the chipset specified
size is ignored. Print a warning for that, especially because v2 uses
the chipset specified RAM size.
Build and boot tested on qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@766 f3766cd6-281f-0410-b1cd-43a5c92072e9
This is not nearly complete, but just the current state of my tree.
k8/raminit.c does not compile at all. Lots of fixes are still needed to bring
it working into v3. I've gone through about 1/8 of the file, it errors out on
line 576 now.
The mcp55 files are in a very early state and also do not compile for me, so
I've disabled them by commenting out the select in mainboard/gigabyte/Kconfig.
Once northbridge/amd/k8/raminit.c builds, k8_ops needs to be added, then we
may actually see the first v3 k8 build. :)
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@713 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@712 f3766cd6-281f-0410-b1cd-43a5c92072e9
removed the ELF loader from coreboot v3. This adds a Kconfig option
PAYLOAD_ELF_LOADER which builds the loader into v3. In order to make it a
little safer, I changed PAYLOAD_PREPARSE_ELF to PAYLOAD_NO_PREPARSE_ELF and
made that option depend on PAYLOAD_ELF_LOADER so that no one adds an unparsed
ELF without the loader.
One part that was strange to me was that I first tried adding elfboot.o and
archelfboot.o to the beginning of the list of object files. I added them to
the end of the list instead.
Myles
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@640 f3766cd6-281f-0410-b1cd-43a5c92072e9
adding a payload. It depends on having a payload so that you can't
end up with a file with no payload and no possiblility to add one.
The default is no zero-filling.
I also added a message "ZEROING lar -z ./coreboot.rom"
Myles
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@621 f3766cd6-281f-0410-b1cd-43a5c92072e9
makes the default to parse the ELF, but leaves ELF parsing available. It
doesn't include the removal of the per-file option "nocompress".
Signed-off-by: Myles Watson <mylesgw@gmail.com>
The coreboot part looks OK and is
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@620 f3766cd6-281f-0410-b1cd-43a5c92072e9
- I left LB_TAG_ intact because they are used by the payloads
- file renames are still missing. see next commit
- some lb_ renames might be missing. feel free to provide patches.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@564 f3766cd6-281f-0410-b1cd-43a5c92072e9
how support for superios might look in the future. This code (like all the
rest, too) will certainly change and evolve in the future, as v3 evolves.
-----
Add support for the Fintek F71805f to LinuxBIOSv3. It hasn't been tested yet
because something's failing to build elsewhere, but the stage1 does build, and
for the moment that's what matters. It's based on working v2 code so it should
work fine.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@508 f3766cd6-281f-0410-b1cd-43a5c92072e9
(I think) when the PAYLOAD_NONE change was put in.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@503 f3766cd6-281f-0410-b1cd-43a5c92072e9
These changes extend the larchive structure, and
add a Kconfig EXPERT option to enable the 'no elf' mode.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@483 f3766cd6-281f-0410-b1cd-43a5c92072e9
Will be re-added as soon as we support PowerPC in v3, of course.
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@442 f3766cd6-281f-0410-b1cd-43a5c92072e9
Instead of having lots of almost-empty Kconfig files all over the place,
we now collect all the "book-keeping" information (as opposed to real
LinuxBIOS configuration stuff) in one Kconfig file. The benefits are obvious.
Say we have (at some point in the future) 30 supported northbridges, 30
southbridges, and 30 Super I/O chips. That would make 90 useless Kconfig
files with just one or two lines in them, spread all over the place.
With this new approach we would instead have no additional Kconfig
files, just a list of all 90 supported chip(set)s in one Kconfig file.
For "real" config options we would still use Kconfig files in
(e.g.) southbridge/foo/bar/Kconfig, of course, which are manually "hooked"
into the config system in the top-level Kconfig file.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@441 f3766cd6-281f-0410-b1cd-43a5c92072e9
- Payload file
- No payload
Document the current procedure in the README.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@350 f3766cd6-281f-0410-b1cd-43a5c92072e9
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@325 f3766cd6-281f-0410-b1cd-43a5c92072e9
* fix up device specific code to honour those switches
* quoting fix for xcompile
* drop VGA_CONSOLE as it's not really useful for debugging purposes.
VGA is only set up very late in the boot process, when everything
critical in LinuxBIOS has already been initialized. If LinuxBIOS
fails, you will never see this on the console.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@269 f3766cd6-281f-0410-b1cd-43a5c92072e9
southbridge drivers in Kconfig.
* It includes initial superio code as well, but there is at least one
error in the pnp_device.c/superio scenario left
* Fixed biosemu.c, vm86.c, pnp_device.c (sort of)
* Enable vm86 instead of x86emu per default for vga init for now. This
makes VGA in qemu work. There might be a bug in x86emu or the compiler
I am using. (gcc version 4.1.2 20070115 (prerelease) (SUSE Linux))
* Import isa-dma.c, keyboard.c and i8259.c from v2 /pc80, which was taken
from LinuxBIOSv1 released from LANL under release LA-CC Number 00-34
and using parts from the Linux kernel.
This patch makes vga and keyboard work in qemu. Yippie
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@260 f3766cd6-281f-0410-b1cd-43a5c92072e9
it via Kconfig (select box with some common values).
The default is 256 KB.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@196 f3766cd6-281f-0410-b1cd-43a5c92072e9
- EXPERIMENTAL - enable experimental/incomplete code/boards
- EXPERT - enable expert/developer options
- LOCALVERSION - set a string to append to the LinuxBIOS version
Mark BOARD_EMULATION_QEMU_POWERPC and CONSOLE_USB as experimental for now.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@184 f3766cd6-281f-0410-b1cd-43a5c92072e9
* small warnings fixes
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@93 f3766cd6-281f-0410-b1cd-43a5c92072e9
* fix arch/io.h to use consistent types
* add compression code and start integration into Kconfig
* update to newer version of Kconfig, and rename some occurences
of "Linux" to "LinuxBIOS"
* set up Make framework to create linuxbios.rom
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G Minnich <rminnich@lanl.gov>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@55 f3766cd6-281f-0410-b1cd-43a5c92072e9
