SAROO/FPGA/cdc_fifo/fifo4k.qip
2015-06-08 22:31:29 +08:00

4 lines
269 B
Text

set_global_assignment -name IP_TOOL_NAME "FIFO"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fifo4k.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo4k_bb.v"]