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add FPGA code

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tpunix 2015-06-08 22:31:29 +08:00
parent f9e0c14740
commit fa4c9dfe25
18 changed files with 3691 additions and 0 deletions
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 11:32:21 July 16, 2014
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "11:32:21 July 16, 2014"
# Revisions
PROJECT_REVISION = "SSMaster"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 11:32:21 July 16, 2014
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# SSMaster_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6F17C8
set_global_assignment -name TOP_LEVEL_ENTITY SSMaster
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:32:21 JULY 16, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_R5 -to SD_ADDR[12]
set_location_assignment PIN_T5 -to SD_ADDR[11]
set_location_assignment PIN_M7 -to SD_ADDR[10]
set_location_assignment PIN_R6 -to SD_ADDR[9]
set_location_assignment PIN_T6 -to SD_ADDR[8]
set_location_assignment PIN_R7 -to SD_ADDR[7]
set_location_assignment PIN_T7 -to SD_ADDR[6]
set_location_assignment PIN_R8 -to SD_ADDR[5]
set_location_assignment PIN_T8 -to SD_ADDR[4]
set_location_assignment PIN_L8 -to SD_ADDR[3]
set_location_assignment PIN_M8 -to SD_ADDR[2]
set_location_assignment PIN_P8 -to SD_ADDR[1]
set_location_assignment PIN_N8 -to SD_ADDR[0]
set_location_assignment PIN_P6 -to SD_BA[1]
set_location_assignment PIN_N6 -to SD_BA[0]
set_location_assignment PIN_P3 -to SD_CAS
set_location_assignment PIN_T4 -to SD_CKE
set_location_assignment PIN_N5 -to SD_CS
set_location_assignment PIN_L1 -to SD_DQ[15]
set_location_assignment PIN_L2 -to SD_DQ[14]
set_location_assignment PIN_N1 -to SD_DQ[13]
set_location_assignment PIN_N2 -to SD_DQ[12]
set_location_assignment PIN_P1 -to SD_DQ[11]
set_location_assignment PIN_P2 -to SD_DQ[10]
set_location_assignment PIN_R1 -to SD_DQ[9]
set_location_assignment PIN_T2 -to SD_DQ[8]
set_location_assignment PIN_K6 -to SD_DQ[7]
set_location_assignment PIN_L4 -to SD_DQ[6]
set_location_assignment PIN_L3 -to SD_DQ[5]
set_location_assignment PIN_K5 -to SD_DQ[4]
set_location_assignment PIN_K2 -to SD_DQ[3]
set_location_assignment PIN_K1 -to SD_DQ[2]
set_location_assignment PIN_J2 -to SD_DQ[1]
set_location_assignment PIN_J1 -to SD_DQ[0]
set_location_assignment PIN_T3 -to SD_DQM[1]
set_location_assignment PIN_N3 -to SD_DQM[0]
set_location_assignment PIN_M6 -to SD_RAS
set_location_assignment PIN_L6 -to SD_WE
set_location_assignment PIN_M1 -to CLK_50M
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name GENERATE_TTF_FILE ON
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_location_assignment PIN_R4 -to SD_CLK
set_location_assignment PIN_R3 -to SD_ADDR[13]
set_location_assignment PIN_J13 -to SS_DATA[2]
set_location_assignment PIN_J12 -to SS_DATA[3]
set_location_assignment PIN_J14 -to SS_DATA[1]
set_location_assignment PIN_J15 -to SS_CS1
set_location_assignment PIN_J16 -to SS_WR1
set_location_assignment PIN_K15 -to SS_ADDR[0]
set_location_assignment PIN_K16 -to SS_RD
set_location_assignment PIN_J11 -to SS_FC1
set_location_assignment PIN_L15 -to SS_ADDR[11]
set_location_assignment PIN_L16 -to SS_ADDR[10]
set_location_assignment PIN_L13 -to SS_AAS
set_location_assignment PIN_L14 -to SS_TIM0
set_location_assignment PIN_N15 -to SS_ADDR[13]
set_location_assignment PIN_N16 -to SS_ADDR[8]
set_location_assignment PIN_R16 -to SS_ADDR[17]
set_location_assignment PIN_P16 -to SS_ADDR[12]
set_location_assignment PIN_P15 -to SS_ADDR[15]
set_location_assignment PIN_K12 -to SS_DATA[0]
set_location_assignment PIN_N14 -to SS_CS2
set_location_assignment PIN_L12 -to SS_FC0
set_location_assignment PIN_M12 -to SS_WR0
set_location_assignment PIN_N13 -to SS_CS0
set_location_assignment PIN_C15 -to SS_DATA[4]
set_location_assignment PIN_C16 -to SS_DATA[5]
set_location_assignment PIN_D15 -to SS_DATA[6]
set_location_assignment PIN_D16 -to SS_DATA[7]
set_location_assignment PIN_G11 -to SS_DATA[8]
set_location_assignment PIN_F14 -to SS_DATA[9]
set_location_assignment PIN_F13 -to SS_DATA[10]
set_location_assignment PIN_B16 -to SS_DATA[15]
set_location_assignment PIN_F15 -to SS_DATA_DIR
set_location_assignment PIN_F16 -to SS_TIM2
set_location_assignment PIN_G15 -to SS_TIM1
set_location_assignment PIN_P14 -to SS_ADDR[1]
set_location_assignment PIN_N12 -to SS_ADDR[2]
set_location_assignment PIN_N11 -to SS_ADDR[3]
set_location_assignment PIN_P11 -to SS_ADDR[4]
set_location_assignment PIN_M10 -to SS_ADDR[5]
set_location_assignment PIN_M9 -to SS_ADDR[6]
set_location_assignment PIN_P9 -to SS_ADDR[7]
set_location_assignment PIN_R14 -to SS_WAIT
set_location_assignment PIN_T15 -to SS_IRQ
set_location_assignment PIN_T14 -to SS_LRCK
set_location_assignment PIN_T13 -to SS_SD
set_location_assignment PIN_R12 -to SS_SSEL
set_location_assignment PIN_R13 -to SS_BCK
set_location_assignment PIN_T12 -to SS_ADDR[16]
set_location_assignment PIN_T11 -to SS_ADDR[21]
set_location_assignment PIN_R11 -to SS_ADDR[18]
set_location_assignment PIN_L9 -to SS_ADDR[19]
set_location_assignment PIN_R10 -to SS_ADDR[20]
set_location_assignment PIN_R9 -to SS_ADDR[22]
set_location_assignment PIN_T9 -to SS_RST
set_location_assignment PIN_D14 -to SS_DATA[11]
set_location_assignment PIN_F11 -to SS_DATA[12]
set_location_assignment PIN_C14 -to SS_DATA[13]
set_location_assignment PIN_A15 -to SS_DATA[14]
set_location_assignment PIN_D11 -to ST_AD[2]
set_location_assignment PIN_D12 -to ST_MCLK
set_location_assignment PIN_B12 -to ST_ADDR[1]
set_location_assignment PIN_A13 -to ST_ADDR[2]
set_location_assignment PIN_B13 -to ST_AD[0]
set_location_assignment PIN_A14 -to ST_AD[1]
set_location_assignment PIN_E11 -to ST_RD
set_location_assignment PIN_B10 -to ST_AD[13]
set_location_assignment PIN_A11 -to ST_AD[14]
set_location_assignment PIN_B11 -to ST_AD[15]
set_location_assignment PIN_A12 -to ST_ADDR[0]
set_location_assignment PIN_C9 -to ST_WAIT
set_location_assignment PIN_E9 -to ST_CS
set_location_assignment PIN_A4 -to ST_AD[4]
set_location_assignment PIN_B5 -to ST_AD[5]
set_location_assignment PIN_A5 -to ST_AD[6]
set_location_assignment PIN_B6 -to ST_AD[7]
set_location_assignment PIN_A6 -to ST_AD[8]
set_location_assignment PIN_B7 -to ST_AD[9]
set_location_assignment PIN_A7 -to ST_AD[10]
set_location_assignment PIN_B8 -to ST_AD[11]
set_location_assignment PIN_A8 -to ST_AD[12]
set_location_assignment PIN_C8 -to ST_BL1
set_location_assignment PIN_E8 -to ST_BL0
set_location_assignment PIN_C6 -to ST_ADDR[4]
set_location_assignment PIN_E7 -to ST_ADDR[3]
set_location_assignment PIN_D6 -to ST_ADDR[5]
set_location_assignment PIN_D5 -to ST_ADDR[6]
set_location_assignment PIN_F1 -to LED0
set_location_assignment PIN_G1 -to LED1
set_location_assignment PIN_M15 -to SS_ADDR[9]
set_location_assignment PIN_E16 -to SS_MCLK
set_location_assignment PIN_M16 -to SS_SCLK
set_location_assignment PIN_N9 -to SS_ADDR[14]
set_location_assignment PIN_C11 -to ST_AD[3]
set_location_assignment PIN_B9 -to ST_BCK
set_location_assignment PIN_A9 -to ST_LRCK
set_location_assignment PIN_D9 -to ST_WR
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_location_assignment PIN_G16 -to FPGA_INIT
set_location_assignment PIN_T10 -to SS_ADDR[23]
set_location_assignment PIN_D8 -to ST_ADDR[7]
set_location_assignment PIN_E1 -to ST_CLK
set_location_assignment PIN_A2 -to ST_GPIO0
set_location_assignment PIN_B3 -to ST_GPIO1
set_location_assignment PIN_A3 -to ST_GPIO2
set_location_assignment PIN_B4 -to ST_GPIO3
set_location_assignment PIN_A10 -to ST_SDO
set_location_assignment PIN_B14 -to SS_DATA_OE
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT ON
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name TRI_STATE_SPI_PINS ON
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE cdc_fifo.stp
set_instance_assignment -name PAD_TO_CORE_DELAY 6 -to ST_GPIO1
set_instance_assignment -name PAD_TO_CORE_DELAY 6 -to ST_CS
set_global_assignment -name SDC_FILE SSMaster.sdc
set_global_assignment -name QSYS_FILE cqsys.qsys
set_global_assignment -name VERILOG_FILE SSMaster.v
set_global_assignment -name SIGNALTAP_FILE fsmc.stp
set_global_assignment -name SIGNALTAP_FILE ss_abus.stp
set_global_assignment -name SIGNALTAP_FILE cdc_fifo.stp
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "cqsys:u0|cdc_fifo:cdc_fifo_0|avm_clk" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to SS_AAS -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to SS_ADDR[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to SS_ADDR[10] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to SS_ADDR[11] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to SS_ADDR[12] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to SS_ADDR[13] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to SS_ADDR[14] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to SS_ADDR[15] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to SS_ADDR[16] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to SS_ADDR[17] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to SS_ADDR[18] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to SS_ADDR[19] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to SS_ADDR[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to SS_ADDR[20] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to SS_ADDR[21] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to SS_ADDR[22] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to SS_ADDR[23] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to SS_ADDR[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to SS_ADDR[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to SS_ADDR[4] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to SS_ADDR[5] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to SS_ADDR[6] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to SS_ADDR[7] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to SS_ADDR[8] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to SS_ADDR[9] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to SS_CS2 -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to SS_DATA[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to SS_DATA[10] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to SS_DATA[11] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to SS_DATA[12] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to SS_DATA[13] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to SS_DATA[14] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to SS_DATA[15] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to SS_DATA[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to SS_DATA[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to SS_DATA[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to SS_DATA[4] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to SS_DATA[5] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to SS_DATA[6] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to SS_DATA[7] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to SS_DATA[8] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to SS_DATA[9] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to SS_FC0 -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to SS_FC1 -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to SS_RD -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to SS_TIM0 -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to SS_TIM1 -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to SS_TIM2 -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to SS_WAIT -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to SS_WR0 -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to SS_WR1 -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to SS_AAS -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to SS_ADDR[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to SS_ADDR[10] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to SS_ADDR[11] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to SS_ADDR[12] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to SS_ADDR[13] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to SS_ADDR[14] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to SS_ADDR[15] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to SS_ADDR[16] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to SS_ADDR[17] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to SS_ADDR[18] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to SS_ADDR[19] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to SS_ADDR[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to SS_ADDR[20] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to SS_ADDR[21] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to SS_ADDR[22] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to SS_ADDR[23] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to SS_ADDR[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to SS_ADDR[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to SS_ADDR[4] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to SS_ADDR[5] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to SS_ADDR[6] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to SS_ADDR[7] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to SS_ADDR[8] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to SS_ADDR[9] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to SS_CS2 -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to SS_DATA[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to SS_DATA[10] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to SS_DATA[11] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to SS_DATA[12] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to SS_DATA[13] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to SS_DATA[14] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to SS_DATA[15] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to SS_DATA[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to SS_DATA[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to SS_DATA[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to SS_DATA[4] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to SS_DATA[5] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to SS_DATA[6] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to SS_DATA[7] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to SS_DATA[8] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to SS_DATA[9] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to SS_FC0 -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to SS_FC1 -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to SS_RD -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to SS_TIM0 -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to SS_TIM1 -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to SS_TIM2 -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to SS_WAIT -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to SS_WR0 -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to SS_WR1 -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=2048" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=2048" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|avm_rd" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|avm_rdvalid" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|blk_dma_end" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|rd_start" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to ss_rd_start -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to ss_wr_start -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|avm_rd" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|avm_rdvalid" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|blk_dma_end" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[0]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[10]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[11]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[12]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[13]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[14]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[15]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[1]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[2]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[3]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[4]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[5]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[6]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[7]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[8]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|data_out[9]" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "cqsys:u0|cdc_fifo:cdc_fifo_0|rd_start" -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to ss_rd_start -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to ss_wr_start -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=73" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=73" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=244" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=16402" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=33995" -section_id auto_signaltap_0
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name SLD_FILE db/cdc_fifo_auto_stripped.stp

10
FPGA/SSMaster.sdc Normal file
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@ -0,0 +1,10 @@
#**************************************************************
# Create Clock
#**************************************************************
derive_pll_clocks -create_base_clocks
#create_clock -name {CLOCK_50M} -period 20.000 [get_ports {CLK_50M}]

592
FPGA/SSMaster.v Normal file
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@ -0,0 +1,592 @@
///////////////////////////////////////////////////////
// Module: SEGA Saturn Master Flash Card //
///////////////////////////////////////////////////////
// version 0.1: first step.
module SSMaster(
// System
CLK_50M,
// SDRAM
SD_CKE, SD_CLK, SD_CS, SD_WE, SD_CAS, SD_RAS, SD_ADDR, SD_BA, SD_DQM, SD_DQ,
// SS system
SS_MCLK, SS_RST,
// SS I2S output
SS_SCLK, SS_SSEL, SS_BCK, SS_LRCK, SS_SD,
// SS ABUS
SS_FC0, SS_FC1, SS_TIM0, SS_TIM1, SS_TIM2, SS_AAS,
SS_ADDR, SS_DATA, SS_CS0, SS_CS1, SS_CS2, SS_RD, SS_WR0, SS_WR1, SS_WAIT, SS_IRQ,
SS_DATA_OE, SS_DATA_DIR,
// STM32 FSMC
ST_CLK, ST_AD, ST_ADDR, ST_CS, ST_RD, ST_WR, ST_BL0, ST_BL1, ST_WAIT,
// STM32 GPIO
ST_GPIO0, ST_GPIO1, ST_GPIO2, ST_GPIO3,
// STM32 I2S
ST_MCLK, ST_BCK, ST_LRCK, ST_SDO,
// DEBUG LED
LED0, LED1
);
///////////////////////////////////////////////////////
// Pins //
///////////////////////////////////////////////////////
// System
input CLK_50M;
// SDRAM
output SD_CKE;
output SD_CLK;
output SD_CS;
output SD_WE;
output SD_CAS;
output SD_RAS;
output[13:0] SD_ADDR;
output[ 1:0] SD_BA;
output[ 1:0] SD_DQM;
inout[15:0] SD_DQ;
// SS System
input SS_MCLK;
input SS_RST;
// SS I2S
input SS_SCLK;
output SS_SSEL;
output SS_BCK;
output SS_LRCK;
output SS_SD;
// SS ABUS
input SS_FC0;
input SS_FC1;
input SS_TIM0;
input SS_TIM1;
input SS_TIM2;
input SS_AAS;
input[23:0] SS_ADDR;
inout[15:0] SS_DATA;
input SS_CS0;
input SS_CS1;
input SS_CS2;
input SS_RD;
input SS_WR0;
input SS_WR1;
output SS_WAIT;
output SS_IRQ;
output SS_DATA_OE;
output SS_DATA_DIR;
// STM32 FSMC
input ST_CLK;
inout[15:0] ST_AD;
input[ 7:0] ST_ADDR;
input ST_CS;
input ST_RD;
input ST_WR;
input ST_BL0;
input ST_BL1;
output ST_WAIT;
// STM32 GPIO
input ST_GPIO0;
input ST_GPIO1;
output ST_GPIO2;
input ST_GPIO3;
// STM32 I2S
output ST_MCLK;
input ST_BCK;
input ST_LRCK;
input ST_SDO;
// DEBUG LED
output LED0;
output LED1;
///////////////////////////////////////////////////////
// Debug LED //
///////////////////////////////////////////////////////
assign LED0 = SS_WAIT;
assign LED1 = ss_reg_ctrl[8];
wire NRESET = ST_GPIO0;
wire ST_ALE = ST_GPIO1;
assign ST_GPIO2 = ST_IRQ;
///////////////////////////////////////////////////////
// I2S //
///////////////////////////////////////////////////////
assign ST_MCLK = SS_SCLK;
assign SS_BCK = ST_BCK;
assign SS_LRCK = ST_LRCK;
assign SS_SD = ST_SDO;
///////////////////////////////////////////////////////
// STM32 FSMC //
///////////////////////////////////////////////////////
// fsmc address latch
reg[24:0] fsmc_addr;
reg fsmc_cs;
always @(posedge ST_ALE)
begin
fsmc_addr <= {ST_ADDR, ST_AD, 1'b0};
end
always @(posedge ST_CS or posedge ST_ALE)
begin
if(ST_CS==1)
fsmc_cs <= 1;
else
fsmc_cs <= 0;
end
// fsmc read sync
reg stale_s0, stale_s1, stale_s2;
always @(posedge avm_clk)
begin
stale_s0 <= ST_ALE;
stale_s1 <= stale_s0;
stale_s2 <= stale_s1;
end
// rising edge of ale
wire st_rd_start = (stale_s2==0 && stale_s1==1 && ST_WR==1);
// fsmc write sync
reg stnwr_s0, stnwr_s1, stnwr_s2;
always @(posedge avm_clk)
begin
stnwr_s0 <= ST_WR;
stnwr_s1 <= stnwr_s0;
stnwr_s2 <= stnwr_s1;
end
wire st_wr_start = (stnwr_s2==1 && stnwr_s1==0); // falling edge of wr
///////////////////////////////////////////////////////
// STM32 FPGA control register //
///////////////////////////////////////////////////////
reg[15:0] st_reg_ctrl;
reg[15:0] ss_resp1;
reg[15:0] ss_resp2;
reg[15:0] ss_resp3;
reg[15:0] ss_resp4;
reg[31:0] st_reg_blk_addr;
reg[15:0] st_reg_blk_size;
reg[15:0] st_reg_fifo_ctrl;
always @(negedge NRESET or posedge avm_clk)
begin
if(NRESET==0) begin
st_reg_ctrl <= 0;
end else if(st_wr_start==1) begin
if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h04) st_reg_ctrl <= ST_AD;
if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h08) st_reg_blk_addr[15:0] <= ST_AD;
if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h0a) st_reg_blk_addr[31:16] <= ST_AD;
if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h0c) st_reg_blk_size <= ST_AD;
if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h10) st_reg_fifo_ctrl <= ST_AD;
if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h20) ss_resp1 <= ST_AD;
if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h22) ss_resp2 <= ST_AD;
if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h24) ss_resp3 <= ST_AD;
if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h26) ss_resp4 <= ST_AD;
end
end
///////////////////////////////////////////////////////
// Saturn to STM32: HIRQ register //
///////////////////////////////////////////////////////
reg[15:0] ss_hirq;
always @(negedge NRESET or posedge avm_clk)
begin
if(NRESET==0) begin
ss_hirq <= 0;
end else begin
if( st_wr_start==1 && fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h28)
ss_hirq <= ss_hirq|ST_AD;
else if(st_wr_start==1 && fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h16)
ss_hirq <= ss_hirq&(~ST_AD);
else if(ss_wr_start==1 && ss_cdc_cs==1 && SS_ADDR[5:2]==4'b00_10)
ss_hirq <= ss_hirq&SS_DATA;
end
end
///////////////////////////////////////////////////////
// Saturn to STM32: CDC request //
///////////////////////////////////////////////////////
reg st_irq_cdc;
always @(negedge NRESET or posedge avm_clk)
begin
if(NRESET==0) begin
st_irq_cdc <= 1'b0;
end else begin
if(ss_wr_start==1 && ss_cdc_cs==1 && SS_ADDR[5:2]==4'b10_01)
st_irq_cdc <= 1'b1;
else if(st_wr_start==1 && fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h06)
st_irq_cdc <= st_irq_cdc&(~ST_AD[0]);
end
end
///////////////////////////////////////////////////////
// Saturn to STM32: CMD request //
///////////////////////////////////////////////////////
reg st_irq_cmd;
always @(negedge NRESET or posedge avm_clk)
begin
if(NRESET==0) begin
st_irq_cmd <= 1'b0;
end else begin
if(ss_wr_start==1 && ss_reg_cs==1 && SS_ADDR[5:1]==5'b00_110)
st_irq_cmd <= 1'b1;
else if(st_wr_start==1 && fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h06)
st_irq_cmd <= st_irq_cmd&(~ST_AD[1]);
end
end
///////////////////////////////////////////////////////
// CDC FIFO dma end //
///////////////////////////////////////////////////////
reg st_irq_fifo;
always @(negedge NRESET or posedge avm_clk)
begin
if(NRESET==0) begin
st_irq_fifo <= 1'b0;
end else begin
if(fifo_blk_dma_end==1)
st_irq_fifo <= 1'b1;
else if(st_wr_start==1 && fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h06)
st_irq_fifo <= st_irq_fifo&(~ST_AD[2]);
end
end
///////////////////////////////////////////////////////
// Saturn to STM32: CR4 read //
///////////////////////////////////////////////////////
reg st_irq_cr4rd;
always @(negedge NRESET or posedge avm_clk)
begin
if(NRESET==0) begin
st_irq_cr4rd <= 1'b0;
end else begin
if(ss_rd_start==1 && ss_cdc_cs==1 && SS_ADDR[5:2]==4'b10_01)
st_irq_cr4rd <= 1'b1;
else if(st_wr_start==1 && fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h06)
st_irq_cr4rd <= st_irq_cr4rd&(~ST_AD[3]);
end
end
///////////////////////////////////////////////////////
// STM32 read data //
///////////////////////////////////////////////////////
reg[15:0] st_reg_data_out;
always @(posedge avm_clk)
begin
st_reg_data_out <=
(fsmc_addr[7:0]==8'h00)? 16'h5253 : // ID: "SR"
(fsmc_addr[7:0]==8'h02)? 16'h1101 : // ver: HW1.1 && SW0.1
(fsmc_addr[7:0]==8'h04)? st_reg_ctrl :
(fsmc_addr[7:0]==8'h06)? st_reg_stat :
(fsmc_addr[7:0]==8'h08)? st_reg_blk_addr[15: 0] :
(fsmc_addr[7:0]==8'h0a)? st_reg_blk_addr[31:16] :
(fsmc_addr[7:0]==8'h0c)? st_reg_blk_size :
(fsmc_addr[7:0]==8'h10)? st_reg_fifo_ctrl :
(fsmc_addr[7:0]==8'h12)? st_reg_fifo_stat :
(fsmc_addr[7:0]==8'h14)? ss_reg_ctrl :
(fsmc_addr[7:0]==8'h18)? ss_resp1 :
(fsmc_addr[7:0]==8'h1a)? ss_resp2 :
(fsmc_addr[7:0]==8'h1c)? ss_resp3 :
(fsmc_addr[7:0]==8'h1e)? ss_resp4 :
(fsmc_addr[7:0]==8'h20)? ss_cr1 :
(fsmc_addr[7:0]==8'h22)? ss_cr2 :
(fsmc_addr[7:0]==8'h24)? ss_cr3 :
(fsmc_addr[7:0]==8'h26)? ss_cr4 :
(fsmc_addr[7:0]==8'h28)? ss_hirq :
(fsmc_addr[7:0]==8'h2a)? ss_hirq_mask :
(fsmc_addr[7:0]==8'h2c)? ss_mrgb :
(fsmc_addr[7:0]==8'h2e)? ss_reg_cmd :
(fsmc_addr[7:0]==8'h30)? fifo_rd_times[15: 0] :
(fsmc_addr[7:0]==8'h32)? fifo_rd_times[31:16] :
16'hffff;
end
assign ST_AD = (ST_RD==0 && ST_CS==0)? (
(fsmc_addr[24]==0)? st_reg_data_out : st_ram_data_out
) : 16'hzzzz;
wire st_ram_cs = !(fsmc_cs==0 && ST_ADDR[7]==1);
wire[15:0] st_reg_stat;
assign st_reg_stat = {pll_locked, ST_IRQ, 10'b0, st_irq_cr4rd, st_irq_fifo, st_irq_cmd, st_irq_cdc};
wire st_irq_cr4en = st_reg_ctrl[3];
wire st_irq_fifoen = st_reg_ctrl[2];
wire st_irq_cmd_en = st_reg_ctrl[1];
wire st_irq_cdc_en = st_reg_ctrl[0];
wire ST_IRQ = ( (st_irq_cdc_en==1 && st_irq_cdc==1) ||
(st_irq_cmd_en==1 && st_irq_cmd==1) ||
(st_irq_cr4en ==1 && st_irq_cr4rd==1) ||
(st_irq_fifoen==1 && st_irq_fifo==1) );
///////////////////////////////////////////////////////
// SATURN ABUS //
///////////////////////////////////////////////////////
reg sscs_s0, sscs_s1, sscs_s2, sscs_s3, sscs_s4;
always @(posedge avm_clk)
begin
sscs_s0 <= (SS_CS0 & SS_CS1 & SS_CS2);
sscs_s1 <= sscs_s0;
sscs_s2 <= sscs_s1;
sscs_s3 <= sscs_s2;
sscs_s4 <= sscs_s3;
end
wire ss_rd_start = (sscs_s2==1 && sscs_s1==0 && SS_RD==0);
wire ss_wr_start = (sscs_s4==1 && sscs_s3==0 && (SS_WR0==0 || SS_WR1==0));
assign SS_DATA =(SS_RD==0 && SS_CS0==0)? ss_ram_data_out :
(SS_RD==0 && SS_CS1==0)? ss_cs1_data_out :
(SS_RD==0 && ss_reg_cs==1)? ss_bcr_data_out :
(SS_RD==0 && ss_cdc_cs==1)? ss_cdc_data_out :
16'hzzzz;
assign SS_DATA_OE = (SS_CS0==1 && SS_CS1==1 && (SS_CS2==1 || (ss_cdc_cs==1 && SS_RD==0 && ss_cdc_en==0)));
assign SS_DATA_DIR = (SS_WR0 & SS_WR1);
///////////////////////////////////////////////////////
// SATURN System Control //
///////////////////////////////////////////////////////
reg[15:0] ss_bcr_data_out;
reg[15:0] ss_reg_ctrl;
reg[15:0] ss_reg_cmd;
reg[31:0] ss_reg_timer;
// 00: None
// 01: Data Cart
// 10: RAM Cart: 1MBytes
// 11: RAM Cart: 4MBytes
wire[1:0] ss_cs0_type = ss_reg_ctrl[13:12];
wire ss_reg_cs = (SS_CS2==0 && SS_ADDR[14:12]==3'b111);
wire[15:0] ss_cs1_data_out = (SS_ADDR[23:16]==8'hff && ss_cs0_type[1]==1)?
(
(ss_cs0_type[0]==0)? 16'hff5a : 16'hff5c
) : ss_ram_data_out;
always @(posedge avm_clk)
begin
ss_bcr_data_out <=
(SS_ADDR[5:1]==5'b00_000)? 16'h5253 : // ID: "SR"
(SS_ADDR[5:1]==5'b00_001)? 16'h1101 : // ver: HW1.1 && SW0.1
(SS_ADDR[5:1]==5'b00_010)? ss_reg_ctrl :
(SS_ADDR[5:1]==5'b00_100)? ss_reg_timer[31:16] :
(SS_ADDR[5:1]==5'b00_101)? ss_reg_timer[15: 0] :
(SS_ADDR[5:1]==5'b00_110)? ss_reg_cmd :
16'h0000;
end
always @(negedge NRESET or posedge avm_clk)
begin
if(NRESET==0)
ss_reg_ctrl <= 16'h0100;
else if(ss_wr_start==1 && ss_reg_cs==1 && SS_ADDR[5:1]==5'b00_010)
ss_reg_ctrl <= SS_DATA;
end
always @(negedge NRESET or posedge avm_clk)
begin
if(NRESET==0)
ss_reg_cmd <= 4'b0000;
else if(st_wr_start==1 && fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h2e)
ss_reg_cmd <= 0;
else if(ss_wr_start==1 && ss_reg_cs==1 && SS_ADDR[5:1]==5'b00_110)
ss_reg_cmd <= SS_DATA;
end
reg[6:0] ss_timer_feed;
always @(posedge avm_clk)
begin
if(ss_timer_feed==7'd99)
ss_timer_feed <= 0;
else
ss_timer_feed <= ss_timer_feed+7'b1;
end
always @(posedge avm_clk)
begin
if(ss_wr_start==1 && ss_reg_cs==1 && SS_ADDR[5:1]==5'b00_100)
ss_reg_timer <= 0;
else if(ss_timer_feed==0) begin
ss_reg_timer <= ss_reg_timer+32'b1;
end
end
///////////////////////////////////////////////////////
// SATURN CDC //
///////////////////////////////////////////////////////
reg[15:0] ss_cdc_data_out;
reg[15:0] ss_hirq_mask;
reg[15:0] ss_cr1;
reg[15:0] ss_cr2;
reg[15:0] ss_cr3;
reg[15:0] ss_cr4;
reg[15:0] ss_mrgb;
// enable CDC read out
wire ss_cdc_en = ss_reg_ctrl[15];
wire ss_cdc_cs = (SS_CS2==0 && SS_ADDR[14:12]==3'b000);
wire ss_cdc_data = (ss_cdc_cs==1 && SS_ADDR[5:2]==0);
always @(posedge avm_clk)
begin
if(ss_wr_start==1 && ss_cdc_cs==1) begin
if(SS_ADDR[5:2]==4'b00_11) ss_hirq_mask <= SS_DATA;
if(SS_ADDR[5:2]==4'b01_10) ss_cr1 <= SS_DATA;
if(SS_ADDR[5:2]==4'b01_11) ss_cr2 <= SS_DATA;
if(SS_ADDR[5:2]==4'b10_00) ss_cr3 <= SS_DATA;
if(SS_ADDR[5:2]==4'b10_01) ss_cr4 <= SS_DATA;
if(SS_ADDR[5:2]==4'b10_10) ss_mrgb <= SS_DATA;
end
end
always @(posedge avm_clk)
begin
ss_cdc_data_out <=
(SS_ADDR[5:2]==4'b00_00)? ss_fifo_data_out :
(SS_ADDR[5:2]==4'b00_10)? ss_hirq :
(SS_ADDR[5:2]==4'b00_11)? ss_hirq_mask :
(SS_ADDR[5:2]==4'b01_10)? ss_resp1 :
(SS_ADDR[5:2]==4'b01_11)? ss_resp2 :
(SS_ADDR[5:2]==4'b10_00)? ss_resp3 :
(SS_ADDR[5:2]==4'b10_01)? ss_resp4 :
(SS_ADDR[5:2]==4'b10_10)? ss_mrgb :
16'h0000;
end
assign SS_SSEL = ~ss_cdc_en;
assign SS_IRQ = (ss_hirq&ss_hirq_mask)==0? 1'b0: 1'b1;
///////////////////////////////////////////////////////////////////////////////////////////////////
// FIFO test
reg[31:0] fifo_rd_times;
always @(posedge avm_clk)
begin
if(st_wr_start==1 && fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h30)
fifo_rd_times <= 0;
else if(ss_rd_start==1 && ss_cdc_data==1) begin
fifo_rd_times <= fifo_rd_times+32'b1;
end
end
///////////////////////////////////////////////////////
// QSYS //
///////////////////////////////////////////////////////
wire avm_clk;
wire pll_locked;
wire[15:0] st_ram_data_out;
wire[15:0] ss_ram_din = {SS_DATA[7:0], SS_DATA[15:8]};
wire[15:0] ss_ram_dout;
wire[15:0] ss_ram_data_out = {ss_ram_dout[7:0], ss_ram_dout[15:8]};
wire[15:0] ss_fifo_dout;
wire[15:0] ss_fifo_data_out = {ss_fifo_dout[7:0], ss_fifo_dout[15:8]};
wire[15:0] st_reg_fifo_stat;
wire fifo_blk_dma_end;
cqsys u0 (
.clk_clk (CLK_50M),
.reset_reset_n (NRESET),
.avm_clk_clk (avm_clk),
.mem_pin_addr (SD_ADDR),
.mem_pin_ba (SD_BA),
.mem_pin_cas_n (SD_CAS),
.mem_pin_cke (SD_CKE),
.mem_pin_cs_n (SD_CS),
.mem_pin_dq (SD_DQ),
.mem_pin_dqm (SD_DQM),
.mem_pin_ras_n (SD_RAS),
.mem_pin_we_n (SD_WE),
.fsmc_bus_addr ({8'b0, fsmc_addr[23:0]}),
.fsmc_bus_ncs (st_ram_cs),
.fsmc_bus_rd_start (st_rd_start),
.fsmc_bus_wr_start (st_wr_start),
.fsmc_bus_byte_en ({~ST_BL1, ~ST_BL0}),
.fsmc_bus_data_in (ST_AD),
.fsmc_bus_data_out (st_ram_data_out),
.fsmc_bus_wait_out (ST_WAIT),
.saturn_bus_addr ({7'b0, ~SS_CS1, SS_ADDR}),
.saturn_bus_ncs (SS_CS0&SS_CS1),
.saturn_bus_rd_start (ss_rd_start),
.saturn_bus_wr_start (ss_wr_start),
.saturn_bus_byte_en ({~SS_WR0, ~SS_WR1}),
.saturn_bus_data_in (ss_ram_din),
.saturn_bus_data_out (ss_ram_dout),
.saturn_bus_wait_out (SS_WAIT),
.cdc_fifo_reg_fifo_ctrl (st_reg_fifo_ctrl),
.cdc_fifo_reg_fifo_stat (st_reg_fifo_stat),
.cdc_fifo_reg_blk_addr (st_reg_blk_addr),
.cdc_fifo_reg_blk_size (st_reg_blk_size),
.cdc_fifo_rd_start ((ss_rd_start==1 && ss_cdc_data==1)),
.cdc_fifo_data_out (ss_fifo_dout),
.cdc_fifo_blk_dma_end (fifo_blk_dma_end),
.altpll_locked_export (pll_locked)
);
assign SD_CLK = avm_clk;
endmodule

805
FPGA/SSMaster_assignment_defaults.qdf Normal file
View file

@ -0,0 +1,805 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 09:35:03 September 25, 2014
#
# -------------------------------------------------------------------------- #
#
# Note:
#
# 1) Do not modify this file. This file was generated
# automatically by the Quartus II software and is used
# to preserve global assignments across Quartus II versions.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
set_global_assignment -name SMART_RECOMPILE Off
set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
set_global_assignment -name HC_OUTPUT_DIR hc_output
set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
set_global_assignment -name REVISION_TYPE Base
set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
set_global_assignment -name DO_COMBINED_ANALYSIS Off
set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000B
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy II"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000AE
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family Cyclone
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy III"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000S
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone II"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy IV"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria GX"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX3000A
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II"
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family Stratix
set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix
set_global_assignment -name MUX_RESTRUCTURE Auto
set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
set_global_assignment -name ENABLE_IP_DEBUG Off
set_global_assignment -name SAVE_DISK_SPACE On
set_global_assignment -name DISABLE_OCP_HW_EVAL Off
set_global_assignment -name DEVICE_FILTER_PACKAGE Any
set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
set_global_assignment -name FAMILY "Cyclone IV GX"
set_global_assignment -name TRUE_WYSIWYG_FLOW Off
set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
set_global_assignment -name STATE_MACHINE_PROCESSING Auto
set_global_assignment -name SAFE_STATE_MACHINE Off
set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
set_global_assignment -name PARALLEL_SYNTHESIS On
set_global_assignment -name DSP_BLOCK_BALANCING Auto
set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
set_global_assignment -name NOT_GATE_PUSH_BACK On
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
set_global_assignment -name IGNORE_CARRY_BUFFERS Off
set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
set_global_assignment -name IGNORE_LCELL_BUFFERS Off
set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
set_global_assignment -name IGNORE_SOFT_BUFFERS On
set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
set_global_assignment -name AUTO_GLOBAL_OE_MAX On
set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
set_global_assignment -name ALLOW_XOR_GATE_USAGE On
set_global_assignment -name AUTO_LCELL_INSERTION On
set_global_assignment -name CARRY_CHAIN_LENGTH 48
set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
set_global_assignment -name CASCADE_CHAIN_LENGTH 2
set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
set_global_assignment -name AUTO_CARRY_CHAINS On
set_global_assignment -name AUTO_CASCADE_CHAINS On
set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
set_global_assignment -name AUTO_ROM_RECOGNITION On
set_global_assignment -name AUTO_RAM_RECOGNITION On
set_global_assignment -name AUTO_DSP_RECOGNITION On
set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
set_global_assignment -name STRICT_RAM_RECOGNITION Off
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
set_global_assignment -name FORCE_SYNCH_CLEAR Off
set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
set_global_assignment -name AUTO_RESOURCE_SHARING Off
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
set_global_assignment -name MAX7000_FANIN_PER_CELL 100
set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy III"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Cyclone II"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "HardCopy II"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy IV"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III LS"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix III"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria VI"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix VI"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Arria GX"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II GX"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
set_global_assignment -name REPORT_PARAMETER_SETTINGS On
set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "HardCopy II"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix VI"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family Cyclone
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix II GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "HardCopy III"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone II"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "HardCopy IV"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III LS"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix III"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria VI"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Arria GX"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix II"
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family Stratix
set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
set_global_assignment -name HDL_MESSAGE_LEVEL Level2
set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
set_global_assignment -name BLOCK_DESIGN_NAMING Auto
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
set_global_assignment -name SYNTHESIS_EFFORT Auto
set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy III"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone II"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy II"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy IV"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria VI"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix VI"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Cyclone
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix II"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Stratix
set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
set_global_assignment -name MAX_LABS "-1 (Unlimited)"
set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
set_global_assignment -name SYNTHESIS_SEED 1
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
set_global_assignment -name AUTO_PARALLEL_SYNTHESIS Off
set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
set_global_assignment -name AUTO_MERGE_PLLS On
set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
set_global_assignment -name TXPMA_SLEW_RATE Low
set_global_assignment -name ADCE_ENABLED Auto
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
set_global_assignment -name DEVICE AUTO
set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
set_global_assignment -name ENABLE_NCEO_OUTPUT Off
set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
set_global_assignment -name STRATIX_UPDATE_MODE Standard
set_global_assignment -name CVP_MODE Off
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
set_global_assignment -name USER_START_UP_CLOCK Off
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
set_global_assignment -name ENABLE_VREFA_PIN Off
set_global_assignment -name ENABLE_VREFB_PIN Off
set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
set_global_assignment -name INIT_DONE_OPEN_DRAIN On
set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Cyclone II"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family Cyclone
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II GX"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "HardCopy II"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Arria GX"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
set_global_assignment -name CRC_ERROR_CHECKING Off
set_global_assignment -name INTERNAL_SCRUBBING Off
set_global_assignment -name PR_ERROR_OPEN_DRAIN On
set_global_assignment -name PR_READY_OPEN_DRAIN On
set_global_assignment -name ENABLE_CVP_CONFDONE Off
set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy III"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy IV"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria VI"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix VI"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria GX"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix
set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000B
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy II"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix VI"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000AE
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family Cyclone
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000S
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy III"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone II"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy IV"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III LS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Arria VI"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix III"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria GX"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX3000A
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix II"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family Stratix
set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic
set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
set_global_assignment -name OPTIMIZE_SSN Off
set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
set_global_assignment -name ECO_OPTIMIZE_TIMING Off
set_global_assignment -name ECO_REGENERATE_REPORT Off
set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
set_global_assignment -name SEED 1
set_global_assignment -name SLOW_SLEW_RATE Off
set_global_assignment -name PCI_IO Off
set_global_assignment -name TURBO_BIT On
set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
set_global_assignment -name AUTO_PACKED_REGISTERS Off
set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
set_global_assignment -name NORMAL_LCELL_INSERT On
set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
set_global_assignment -name AUTO_DELAY_CHAINS On
set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
set_global_assignment -name AUTO_TURBO_BIT ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
set_global_assignment -name FITTER_EFFORT "Auto Fit"
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
set_global_assignment -name AUTO_GLOBAL_CLOCK On
set_global_assignment -name AUTO_GLOBAL_OE On
set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
set_global_assignment -name ENABLE_HOLD_BACK_OFF On
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix VI"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "HardCopy III"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria VI"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria VI"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix VI"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
set_global_assignment -name PR_DONE_OPEN_DRAIN On
set_global_assignment -name NCEO_OPEN_DRAIN On
set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
set_global_assignment -name ENABLE_PR_PINS Off
set_global_assignment -name PR_PINS_OPEN_DRAIN Off
set_global_assignment -name CLAMPING_DIODE Off
set_global_assignment -name TRI_STATE_SPI_PINS Off
set_global_assignment -name UNUSED_TSD_PINS_GND Off
set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM
set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
set_global_assignment -name COMPRESSION_MODE Off
set_global_assignment -name CLOCK_SOURCE Internal
set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
set_global_assignment -name SECURITY_BIT Off
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS"
set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II"
set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
set_global_assignment -name GENERATE_TTF_FILE Off
set_global_assignment -name GENERATE_RBF_FILE Off
set_global_assignment -name GENERATE_HEX_FILE Off
set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
set_global_assignment -name AUTO_RESTART_CONFIGURATION On
set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
set_global_assignment -name ENABLE_OCT_DONE Off
set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
set_global_assignment -name START_TIME 0ns
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
set_global_assignment -name SETUP_HOLD_DETECTION Off
set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
set_global_assignment -name CHECK_OUTPUTS Off
set_global_assignment -name SIMULATION_COVERAGE On
set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
set_global_assignment -name GLITCH_DETECTION Off
set_global_assignment -name GLITCH_INTERVAL 1ns
set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
set_global_assignment -name DRC_TOP_FANOUT 50
set_global_assignment -name DRC_FANOUT_EXCEEDING 30
set_global_assignment -name DRC_GATED_CLOCK_FEED 30
set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
set_global_assignment -name ENABLE_DRC_SETTINGS Off
set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
set_global_assignment -name MERGE_HEX_FILE Off
set_global_assignment -name GENERATE_SVF_FILE Off
set_global_assignment -name GENERATE_ISC_FILE Off
set_global_assignment -name GENERATE_JAM_FILE Off
set_global_assignment -name GENERATE_JBC_FILE Off
set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
set_global_assignment -name POWER_USE_PVA On
set_global_assignment -name POWER_USE_INPUT_FILE "No File"
set_global_assignment -name POWER_USE_INPUT_FILES Off
set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
set_global_assignment -name POWER_TJ_VALUE 25
set_global_assignment -name POWER_USE_TA_VALUE 25
set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
set_global_assignment -name POWER_BOARD_TEMPERATURE 25
set_global_assignment -name POWER_HPS_ENABLE Off
set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
set_global_assignment -name IGNORE_PARTITIONS Off
set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
set_global_assignment -name RTLV_GROUP_RELATED_NODES On
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
set_global_assignment -name EQC_BBOX_MERGE On
set_global_assignment -name EQC_LVDS_MERGE On
set_global_assignment -name EQC_RAM_UNMERGING On
set_global_assignment -name EQC_DFF_SS_EMULATION On
set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
set_global_assignment -name EQC_STRUCTURE_MATCHING On
set_global_assignment -name EQC_AUTO_BREAK_CONE On
set_global_assignment -name EQC_POWER_UP_COMPARE Off
set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
set_global_assignment -name EQC_AUTO_INVERSION On
set_global_assignment -name EQC_AUTO_TERMINATE On
set_global_assignment -name EQC_SUB_CONE_REPORT Off
set_global_assignment -name EQC_RENAMING_RULES On
set_global_assignment -name EQC_PARAMETER_CHECK On
set_global_assignment -name EQC_AUTO_PORTSWAP On
set_global_assignment -name EQC_DETECT_DONT_CARES On
set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?

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///////////////////////////////////////////////////////
// Module: SEGA Saturn CDC Data FIFO //
///////////////////////////////////////////////////////
module cdc_fifo(
reg_fifo_ctrl, reg_blk_addr, reg_blk_size, reg_fifo_stat,
rd_start, data_out, blk_dma_end,
avm_clk, avm_reset, avm_addr, avm_rd, avm_rdvalid, avm_rdata, avm_wait
);
///////////////////////////////////////////////////////
// Pins //
///////////////////////////////////////////////////////
input[15:0] reg_fifo_ctrl;
input[31:0] reg_blk_addr;
input[15:0] reg_blk_size;
output[15:0] reg_fifo_stat;
input rd_start;
output[15:0] data_out;
output blk_dma_end;
// avalon master
input avm_clk;
input avm_reset;
output[31:0] avm_addr;
output avm_rd;
input[15:0] avm_rdata;
input avm_rdvalid;
input avm_wait;
///////////////////////////////////////////////////////
// FIFO //
///////////////////////////////////////////////////////
wire[10:0] usedw;
wire full;
wire empty;
wire fifo_reset = reg_fifo_ctrl[2];
fifo4k f4k(
.aclr (fifo_reset),
.clock (avm_clk),
.rdreq (rd_start),
.q (data_out),
.wrreq (avm_rdvalid),
.data (avm_rdata),
.empty (empty),
.full (full),
.usedw (usedw)
);
wire[15:0] reg_fifo_stat = {mstate, empty, full, usedw};
///////////////////////////////////////////////////////
// master state //
///////////////////////////////////////////////////////
reg[2:0] mstate;
reg[15:0] dma_count;
reg[31:0] avm_addr;
reg avm_rd;
reg blk_dma_end;
wire dma_start = reg_fifo_ctrl[0];
wire dma_abort = reg_fifo_ctrl[1];
localparam M_IDLE=3'd0, M_LOAD=3'd1, M_READ_START=3'd2, M_READ_WAIT=3'd3, M_READ_NEXT=3'd4, M_READ_END=3'd5;
always @(posedge avm_reset or posedge avm_clk)
begin
if(avm_reset==1) begin
mstate <= M_IDLE;
end else begin
case(mstate)
M_IDLE: begin
if(dma_abort==0 && dma_start==1) begin
mstate <= M_LOAD;
end else begin
blk_dma_end <= 1'b0;
avm_rd <= 0;
end
end
M_LOAD: begin
avm_addr <= reg_blk_addr;
dma_count <= reg_blk_size;
if(dma_abort==1)
mstate <= M_IDLE;
else if(usedw[10:9]==2'b00)
mstate = M_READ_START;
end
M_READ_START: begin
avm_rd <= 1;
mstate <= M_READ_WAIT;
end
M_READ_WAIT: begin
if(avm_wait==0) begin
mstate <= M_READ_NEXT;
avm_rd <= 0;
dma_count <= dma_count-16'd2;
end
end
M_READ_NEXT: begin
avm_addr <= avm_addr+32'd2;
if(dma_abort==1) begin
mstate <= M_IDLE;
end else if(dma_count==0) begin
mstate <= M_READ_END;
end else begin
mstate <= M_READ_START;
end
end
M_READ_END: begin
if(dma_start==0) begin
blk_dma_end <= 1;
mstate <= M_IDLE;
end
end
default: begin
mstate <= M_IDLE;
end
endcase
end
end
endmodule

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# TCL File Generated by Component Editor 13.1
# Wed Nov 19 23:19:19 CST 2014
# DO NOT MODIFY
#
# cdc_fifo "cdc_fifo" v1.0
# tpu 2014.11.19.23:19:18
# Saturn CDC FIFO
#
#
# request TCL package from ACDS 13.1
#
package require -exact qsys 13.1
#
# module cdc_fifo
#
set_module_property DESCRIPTION "Saturn CDC FIFO"
set_module_property NAME cdc_fifo
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Bridges and Adapters/DMA"
set_module_property AUTHOR tpu
set_module_property DISPLAY_NAME cdc_fifo
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL cdc_fifo
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file cdc_fifo.v VERILOG PATH cdc_fifo.v TOP_LEVEL_FILE
add_fileset_file fifo4k.qip OTHER PATH fifo4k.qip
add_fileset_file fifo4k.v VERILOG PATH fifo4k.v
#
# parameters
#
#
# display items
#
#
# connection point conduit_end
#
add_interface conduit_end conduit end
set_interface_property conduit_end associatedClock ""
set_interface_property conduit_end associatedReset ""
set_interface_property conduit_end ENABLED true
set_interface_property conduit_end EXPORT_OF ""
set_interface_property conduit_end PORT_NAME_MAP ""
set_interface_property conduit_end CMSIS_SVD_VARIABLES ""
set_interface_property conduit_end SVD_ADDRESS_GROUP ""
add_interface_port conduit_end reg_fifo_ctrl export Input 16
add_interface_port conduit_end reg_blk_addr export Input 32
add_interface_port conduit_end reg_blk_size export Input 16
add_interface_port conduit_end rd_start export Input 1
add_interface_port conduit_end data_out export Output 16
add_interface_port conduit_end blk_dma_end export Output 1
add_interface_port conduit_end reg_fifo_stat export Output 16
#
# connection point read_master
#
add_interface read_master avalon start
set_interface_property read_master addressUnits SYMBOLS
set_interface_property read_master associatedClock avm_clk
set_interface_property read_master associatedReset avm_reset
set_interface_property read_master bitsPerSymbol 8
set_interface_property read_master burstOnBurstBoundariesOnly false
set_interface_property read_master burstcountUnits WORDS
set_interface_property read_master doStreamReads false
set_interface_property read_master doStreamWrites false
set_interface_property read_master holdTime 0
set_interface_property read_master linewrapBursts false
set_interface_property read_master maximumPendingReadTransactions 0
set_interface_property read_master readLatency 0
set_interface_property read_master readWaitTime 1
set_interface_property read_master setupTime 0
set_interface_property read_master timingUnits Cycles
set_interface_property read_master writeWaitTime 0
set_interface_property read_master ENABLED true
set_interface_property read_master EXPORT_OF ""
set_interface_property read_master PORT_NAME_MAP ""
set_interface_property read_master CMSIS_SVD_VARIABLES ""
set_interface_property read_master SVD_ADDRESS_GROUP ""
add_interface_port read_master avm_addr address Output 32
add_interface_port read_master avm_rd read Output 1
add_interface_port read_master avm_rdvalid readdatavalid Input 1
add_interface_port read_master avm_rdata readdata Input 16
add_interface_port read_master avm_wait waitrequest Input 1
#
# connection point avm_clk
#
add_interface avm_clk clock end
set_interface_property avm_clk clockRate 0
set_interface_property avm_clk ENABLED true
set_interface_property avm_clk EXPORT_OF ""
set_interface_property avm_clk PORT_NAME_MAP ""
set_interface_property avm_clk CMSIS_SVD_VARIABLES ""
set_interface_property avm_clk SVD_ADDRESS_GROUP ""
add_interface_port avm_clk avm_clk clk Input 1
#
# connection point avm_reset
#
add_interface avm_reset reset end
set_interface_property avm_reset associatedClock avm_clk
set_interface_property avm_reset synchronousEdges DEASSERT
set_interface_property avm_reset ENABLED true
set_interface_property avm_reset EXPORT_OF ""
set_interface_property avm_reset PORT_NAME_MAP ""
set_interface_property avm_reset CMSIS_SVD_VARIABLES ""
set_interface_property avm_reset SVD_ADDRESS_GROUP ""
add_interface_port avm_reset avm_reset reset Input 1

4
FPGA/cdc_fifo/fifo4k.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "FIFO"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fifo4k.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo4k_bb.v"]

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FPGA/cdc_fifo/fifo4k.v Normal file
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// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo4k.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo4k (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [15:0] q;
output [10:0] usedw;
wire [10:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire [10:0] usedw = sub_wire0[10:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_empty (),
.almost_full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Cyclone IV E",
scfifo_component.lpm_numwords = 2048,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 16,
scfifo_component.lpm_widthu = 11,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "2048"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "16"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 11 0 OUTPUT NODEFVAL "usedw[10..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: usedw 0 0 11 0 @usedw 0 0 11 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo4k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo4k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo4k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo4k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo4k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo4k_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf

127
FPGA/cdc_fifo/fifo4k_bb.v Normal file
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// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo4k.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo4k (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [15:0] q;
output [10:0] usedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "2048"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "16"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 11 0 OUTPUT NODEFVAL "usedw[10..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: usedw 0 0 11 0 @usedw 0 0 11 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo4k.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo4k.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo4k.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo4k.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo4k_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo4k_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf

20
FPGA/cdc_fifo/greybox_tmp/cbx_args.txt Normal file
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@ -0,0 +1,20 @@
ADD_RAM_OUTPUT_REGISTER=ON
INTENDED_DEVICE_FAMILY="Cyclone IV E"
LPM_NUMWORDS=2048
LPM_SHOWAHEAD=ON
LPM_TYPE=scfifo
LPM_WIDTH=16
LPM_WIDTHU=11
OVERFLOW_CHECKING=ON
UNDERFLOW_CHECKING=ON
USE_EAB=ON
DEVICE_FAMILY="Cyclone IV E"
aclr
clock
data
rdreq
wrreq
empty
full
q
usedw

399
FPGA/cqsys.qsys Normal file
View file

@ -0,0 +1,399 @@
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
}
element FSMC_master
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
element altpll_0
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element cdc_fifo_0
{
datum _sortIndex
{
value = "4";
type = "int";
}
}
element clk_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element new_sdram_controller_0
{
datum _sortIndex
{
value = "5";
type = "int";
}
}
element saturn_master
{
datum _sortIndex
{
value = "3";
type = "int";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="EP4CE6F17C8" />
<parameter name="deviceFamily" value="Cyclone IV E" />
<parameter name="deviceSpeedGrade" value="8" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="SSMaster.qpf" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="0" />
<parameter name="timeStamp" value="0" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
<interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
<interface
name="mem_pin"
internal="new_sdram_controller_0.wire"
type="conduit"
dir="end" />
<interface
name="altpll_locked"
internal="altpll_0.locked_conduit"
type="conduit"
dir="end" />
<interface name="avm_clk" internal="altpll_0.c1" type="clock" dir="start" />
<interface
name="saturn_bus"
internal="saturn_master.ext_bus"
type="conduit"
dir="end" />
<interface
name="fsmc_bus"
internal="FSMC_master.ext_bus"
type="conduit"
dir="end" />
<interface
name="cdc_fifo"
internal="cdc_fifo_0.conduit_end"
type="conduit"
dir="end" />
<module kind="clock_source" version="13.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
<module
kind="altera_avalon_new_sdram_controller"
version="13.1"
enabled="1"
name="new_sdram_controller_0">
<parameter name="TAC" value="6.0" />
<parameter name="TRCD" value="20.0" />
<parameter name="TRFC" value="70.0" />
<parameter name="TRP" value="20.0" />
<parameter name="TWR" value="20.0" />
<parameter name="casLatency" value="2" />
<parameter name="columnWidth" value="9" />
<parameter name="dataWidth" value="16" />
<parameter name="generateSimulationModel" value="false" />
<parameter name="initRefreshCommands" value="8" />
<parameter name="model">single_Micron_MT48LC4M32B2_7_chip</parameter>
<parameter name="numberOfBanks" value="4" />
<parameter name="numberOfChipSelects" value="1" />
<parameter name="pinsSharedViaTriState" value="false" />
<parameter name="powerUpDelay" value="200.0" />
<parameter name="refreshPeriod" value="31.25" />
<parameter name="rowWidth" value="13" />
<parameter name="masteredTristateBridgeSlave" value="0" />
<parameter name="TMRD" value="2" />
<parameter name="initNOPDelay" value="0.0" />
<parameter name="registerDataIn" value="true" />
<parameter name="clockRate" value="100000000" />
<parameter name="componentName">cqsys_new_sdram_controller_0</parameter>
</module>
<module kind="altpll" version="13.1" enabled="1" name="altpll_0">
<parameter name="HIDDEN_CUSTOM_ELABORATION">altpll_avalon_elaboration</parameter>
<parameter name="HIDDEN_CUSTOM_POST_EDIT">altpll_avalon_post_edit</parameter>
<parameter name="INTENDED_DEVICE_FAMILY" value="Cyclone IV E" />
<parameter name="WIDTH_CLOCK" value="5" />
<parameter name="WIDTH_PHASECOUNTERSELECT" value="" />
<parameter name="PRIMARY_CLOCK" value="" />
<parameter name="INCLK0_INPUT_FREQUENCY" value="20000" />
<parameter name="INCLK1_INPUT_FREQUENCY" value="" />
<parameter name="OPERATION_MODE" value="NORMAL" />
<parameter name="PLL_TYPE" value="AUTO" />
<parameter name="QUALIFY_CONF_DONE" value="" />
<parameter name="COMPENSATE_CLOCK" value="CLK0" />
<parameter name="SCAN_CHAIN" value="" />
<parameter name="GATE_LOCK_SIGNAL" value="" />
<parameter name="GATE_LOCK_COUNTER" value="" />
<parameter name="LOCK_HIGH" value="" />
<parameter name="LOCK_LOW" value="" />
<parameter name="VALID_LOCK_MULTIPLIER" value="" />
<parameter name="INVALID_LOCK_MULTIPLIER" value="" />
<parameter name="SWITCH_OVER_ON_LOSSCLK" value="" />
<parameter name="SWITCH_OVER_ON_GATED_LOCK" value="" />
<parameter name="ENABLE_SWITCH_OVER_COUNTER" value="" />
<parameter name="SKIP_VCO" value="" />
<parameter name="SWITCH_OVER_COUNTER" value="" />
<parameter name="SWITCH_OVER_TYPE" value="" />
<parameter name="FEEDBACK_SOURCE" value="" />
<parameter name="BANDWIDTH" value="" />
<parameter name="BANDWIDTH_TYPE" value="AUTO" />
<parameter name="SPREAD_FREQUENCY" value="" />
<parameter name="DOWN_SPREAD" value="" />
<parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
<parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
<parameter name="CLK0_MULTIPLY_BY" value="2" />
<parameter name="CLK1_MULTIPLY_BY" value="2" />
<parameter name="CLK2_MULTIPLY_BY" value="" />
<parameter name="CLK3_MULTIPLY_BY" value="" />
<parameter name="CLK4_MULTIPLY_BY" value="" />
<parameter name="CLK5_MULTIPLY_BY" value="" />
<parameter name="CLK6_MULTIPLY_BY" value="" />
<parameter name="CLK7_MULTIPLY_BY" value="" />
<parameter name="CLK8_MULTIPLY_BY" value="" />
<parameter name="CLK9_MULTIPLY_BY" value="" />
<parameter name="EXTCLK0_MULTIPLY_BY" value="" />
<parameter name="EXTCLK1_MULTIPLY_BY" value="" />
<parameter name="EXTCLK2_MULTIPLY_BY" value="" />
<parameter name="EXTCLK3_MULTIPLY_BY" value="" />
<parameter name="CLK0_DIVIDE_BY" value="1" />
<parameter name="CLK1_DIVIDE_BY" value="1" />
<parameter name="CLK2_DIVIDE_BY" value="" />
<parameter name="CLK3_DIVIDE_BY" value="" />
<parameter name="CLK4_DIVIDE_BY" value="" />
<parameter name="CLK5_DIVIDE_BY" value="" />
<parameter name="CLK6_DIVIDE_BY" value="" />
<parameter name="CLK7_DIVIDE_BY" value="" />
<parameter name="CLK8_DIVIDE_BY" value="" />
<parameter name="CLK9_DIVIDE_BY" value="" />
<parameter name="EXTCLK0_DIVIDE_BY" value="" />
<parameter name="EXTCLK1_DIVIDE_BY" value="" />
<parameter name="EXTCLK2_DIVIDE_BY" value="" />
<parameter name="EXTCLK3_DIVIDE_BY" value="" />
<parameter name="CLK0_PHASE_SHIFT" value="0" />
<parameter name="CLK1_PHASE_SHIFT" value="0" />
<parameter name="CLK2_PHASE_SHIFT" value="" />
<parameter name="CLK3_PHASE_SHIFT" value="" />
<parameter name="CLK4_PHASE_SHIFT" value="" />
<parameter name="CLK5_PHASE_SHIFT" value="" />
<parameter name="CLK6_PHASE_SHIFT" value="" />
<parameter name="CLK7_PHASE_SHIFT" value="" />
<parameter name="CLK8_PHASE_SHIFT" value="" />
<parameter name="CLK9_PHASE_SHIFT" value="" />
<parameter name="EXTCLK0_PHASE_SHIFT" value="" />
<parameter name="EXTCLK1_PHASE_SHIFT" value="" />
<parameter name="EXTCLK2_PHASE_SHIFT" value="" />
<parameter name="EXTCLK3_PHASE_SHIFT" value="" />
<parameter name="CLK0_DUTY_CYCLE" value="50" />
<parameter name="CLK1_DUTY_CYCLE" value="50" />
<parameter name="CLK2_DUTY_CYCLE" value="" />
<parameter name="CLK3_DUTY_CYCLE" value="" />
<parameter name="CLK4_DUTY_CYCLE" value="" />
<parameter name="CLK5_DUTY_CYCLE" value="" />
<parameter name="CLK6_DUTY_CYCLE" value="" />
<parameter name="CLK7_DUTY_CYCLE" value="" />
<parameter name="CLK8_DUTY_CYCLE" value="" />
<parameter name="CLK9_DUTY_CYCLE" value="" />
<parameter name="EXTCLK0_DUTY_CYCLE" value="" />
<parameter name="EXTCLK1_DUTY_CYCLE" value="" />
<parameter name="EXTCLK2_DUTY_CYCLE" value="" />
<parameter name="EXTCLK3_DUTY_CYCLE" value="" />
<parameter name="PORT_clkena0" value="PORT_UNUSED" />
<parameter name="PORT_clkena1" value="PORT_UNUSED" />
<parameter name="PORT_clkena2" value="PORT_UNUSED" />
<parameter name="PORT_clkena3" value="PORT_UNUSED" />
<parameter name="PORT_clkena4" value="PORT_UNUSED" />
<parameter name="PORT_clkena5" value="PORT_UNUSED" />
<parameter name="PORT_extclkena0" value="" />
<parameter name="PORT_extclkena1" value="" />
<parameter name="PORT_extclkena2" value="" />
<parameter name="PORT_extclkena3" value="" />
<parameter name="PORT_extclk0" value="PORT_UNUSED" />
<parameter name="PORT_extclk1" value="PORT_UNUSED" />
<parameter name="PORT_extclk2" value="PORT_UNUSED" />
<parameter name="PORT_extclk3" value="PORT_UNUSED" />
<parameter name="PORT_CLKBAD0" value="PORT_UNUSED" />
<parameter name="PORT_CLKBAD1" value="PORT_UNUSED" />
<parameter name="PORT_clk0" value="PORT_USED" />
<parameter name="PORT_clk1" value="PORT_USED" />
<parameter name="PORT_clk2" value="PORT_UNUSED" />
<parameter name="PORT_clk3" value="PORT_UNUSED" />
<parameter name="PORT_clk4" value="PORT_UNUSED" />
<parameter name="PORT_clk5" value="PORT_UNUSED" />
<parameter name="PORT_clk6" value="" />
<parameter name="PORT_clk7" value="" />
<parameter name="PORT_clk8" value="" />
<parameter name="PORT_clk9" value="" />
<parameter name="PORT_SCANDATA" value="PORT_UNUSED" />
<parameter name="PORT_SCANDATAOUT" value="PORT_UNUSED" />
<parameter name="PORT_SCANDONE" value="PORT_UNUSED" />
<parameter name="PORT_SCLKOUT1" value="" />
<parameter name="PORT_SCLKOUT0" value="" />
<parameter name="PORT_ACTIVECLOCK" value="PORT_UNUSED" />
<parameter name="PORT_CLKLOSS" value="PORT_UNUSED" />
<parameter name="PORT_INCLK1" value="PORT_UNUSED" />
<parameter name="PORT_INCLK0" value="PORT_USED" />
<parameter name="PORT_FBIN" value="PORT_UNUSED" />
<parameter name="PORT_PLLENA" value="PORT_UNUSED" />
<parameter name="PORT_CLKSWITCH" value="PORT_UNUSED" />
<parameter name="PORT_ARESET" value="PORT_UNUSED" />
<parameter name="PORT_PFDENA" value="PORT_UNUSED" />
<parameter name="PORT_SCANCLK" value="PORT_UNUSED" />
<parameter name="PORT_SCANACLR" value="PORT_UNUSED" />
<parameter name="PORT_SCANREAD" value="PORT_UNUSED" />
<parameter name="PORT_SCANWRITE" value="PORT_UNUSED" />
<parameter name="PORT_ENABLE0" value="" />
<parameter name="PORT_ENABLE1" value="" />
<parameter name="PORT_LOCKED" value="PORT_USED" />
<parameter name="PORT_CONFIGUPDATE" value="PORT_UNUSED" />
<parameter name="PORT_FBOUT" value="" />
<parameter name="PORT_PHASEDONE" value="PORT_UNUSED" />
<parameter name="PORT_PHASESTEP" value="PORT_UNUSED" />
<parameter name="PORT_PHASEUPDOWN" value="PORT_UNUSED" />
<parameter name="PORT_SCANCLKENA" value="PORT_UNUSED" />
<parameter name="PORT_PHASECOUNTERSELECT" value="PORT_UNUSED" />
<parameter name="PORT_VCOOVERRANGE" value="" />
<parameter name="PORT_VCOUNDERRANGE" value="" />
<parameter name="DPA_MULTIPLY_BY" value="" />
<parameter name="DPA_DIVIDE_BY" value="" />
<parameter name="DPA_DIVIDER" value="" />
<parameter name="VCO_MULTIPLY_BY" value="" />
<parameter name="VCO_DIVIDE_BY" value="" />
<parameter name="SCLKOUT0_PHASE_SHIFT" value="" />
<parameter name="SCLKOUT1_PHASE_SHIFT" value="" />
<parameter name="VCO_FREQUENCY_CONTROL" value="" />
<parameter name="VCO_PHASE_SHIFT_STEP" value="" />
<parameter name="USING_FBMIMICBIDIR_PORT" value="" />
<parameter name="SCAN_CHAIN_MIF_FILE" value="" />
<parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
<parameter name="HIDDEN_CONSTANTS">CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 2 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_UNUSED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {Cyclone IV E} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 1 CT#PORT_LOCKED PORT_USED</parameter>
<parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 0 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ1 100.00000000 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 8 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT1 0.00000000 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE1 100.000000 PT#EFF_OUTPUT_FREQ_VALUE0 100.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone IV E} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1415009164408010.mif PT#ACTIVECLK_CHECK 0</parameter>
<parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used</parameter>
<parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1</parameter>
<parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
<parameter name="HIDDEN_IF_PORTS">IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#readdata {output 32} IF#write {input 0} IF#phasedone {output 0} IF#address {input 2} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0}</parameter>
<parameter name="HIDDEN_IS_FIRST_EDIT" value="0" />
<parameter name="AUTO_INCLK_INTERFACE_CLOCK_RATE" value="50000000" />
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
</module>
<module kind="ext_master" version="1.0" enabled="1" name="FSMC_master">
<parameter name="AUTO_AVM_CLK_CLOCK_RATE" value="100000000" />
</module>
<module kind="ext_master" version="1.0" enabled="1" name="saturn_master">
<parameter name="AUTO_AVM_CLK_CLOCK_RATE" value="100000000" />
</module>
<module kind="cdc_fifo" version="1.0" enabled="1" name="cdc_fifo_0">
<parameter name="AUTO_AVM_CLK_CLOCK_RATE" value="100000000" />
</module>
<connection
kind="reset"
version="13.1"
start="clk_0.clk_reset"
end="new_sdram_controller_0.reset" />
<connection
kind="reset"
version="13.1"
start="clk_0.clk_reset"
end="altpll_0.inclk_interface_reset" />
<connection
kind="clock"
version="13.1"
start="clk_0.clk"
end="altpll_0.inclk_interface" />
<connection
kind="clock"
version="13.1"
start="altpll_0.c0"
end="new_sdram_controller_0.clk" />
<connection
kind="clock"
version="13.1"
start="altpll_0.c0"
end="FSMC_master.avm_clk" />
<connection
kind="reset"
version="13.1"
start="clk_0.clk_reset"
end="FSMC_master.avm_reset" />
<connection
kind="clock"
version="13.1"
start="altpll_0.c0"
end="saturn_master.avm_clk" />
<connection
kind="reset"
version="13.1"
start="clk_0.clk_reset"
end="saturn_master.avm_reset" />
<connection
kind="avalon"
version="13.1"
start="saturn_master.memory_master"
end="new_sdram_controller_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="avalon"
version="13.1"
start="FSMC_master.memory_master"
end="new_sdram_controller_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<connection
kind="clock"
version="13.1"
start="altpll_0.c0"
end="cdc_fifo_0.avm_clk" />
<connection
kind="reset"
version="13.1"
start="clk_0.clk_reset"
end="cdc_fifo_0.avm_reset" />
<connection
kind="avalon"
version="13.1"
start="cdc_fifo_0.read_master"
end="new_sdram_controller_0.s1">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
<parameter name="defaultConnection" value="false" />
</connection>
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
</system>

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# TCL File Generated by Component Editor 13.1
# Mon Nov 03 17:52:21 CST 2014
# DO NOT MODIFY
#
# FSMC_master "FSMC bus master" v1.0
# tpu 2014.11.03.17:52:21
#
#
#
# request TCL package from ACDS 13.1
#
package require -exact qsys 13.1
#
# module FSMC_master
#
set_module_property DESCRIPTION ""
set_module_property NAME FSMC_master
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP Bridges/Memory-Mapped
set_module_property AUTHOR tpu
set_module_property DISPLAY_NAME "FSMC bus master"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL fsmc_master
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file fsmc_master.v VERILOG PATH fsmc_master.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point avm_clk
#
add_interface avm_clk clock end
set_interface_property avm_clk clockRate 0
set_interface_property avm_clk ENABLED true
set_interface_property avm_clk EXPORT_OF ""
set_interface_property avm_clk PORT_NAME_MAP ""
set_interface_property avm_clk CMSIS_SVD_VARIABLES ""
set_interface_property avm_clk SVD_ADDRESS_GROUP ""
add_interface_port avm_clk avm_clk clk Input 1
#
# connection point avm_reset
#
add_interface avm_reset reset end
set_interface_property avm_reset associatedClock avm_clk
set_interface_property avm_reset synchronousEdges DEASSERT
set_interface_property avm_reset ENABLED true
set_interface_property avm_reset EXPORT_OF ""
set_interface_property avm_reset PORT_NAME_MAP ""
set_interface_property avm_reset CMSIS_SVD_VARIABLES ""
set_interface_property avm_reset SVD_ADDRESS_GROUP ""
add_interface_port avm_reset avm_reset reset Input 1
#
# connection point FSMC_bus
#
add_interface FSMC_bus conduit end
set_interface_property FSMC_bus associatedClock ""
set_interface_property FSMC_bus associatedReset ""
set_interface_property FSMC_bus ENABLED true
set_interface_property FSMC_bus EXPORT_OF ""
set_interface_property FSMC_bus PORT_NAME_MAP ""
set_interface_property FSMC_bus CMSIS_SVD_VARIABLES ""
set_interface_property FSMC_bus SVD_ADDRESS_GROUP ""
add_interface_port FSMC_bus addr export Input 32
add_interface_port FSMC_bus ale export Input 1
add_interface_port FSMC_bus ncs export Input 1
add_interface_port FSMC_bus nrd export Input 1
add_interface_port FSMC_bus nwr export Input 1
add_interface_port FSMC_bus data_in export Input 16
add_interface_port FSMC_bus data_out export Output 16
add_interface_port FSMC_bus wait_out export Output 1
#
# connection point memory_master
#
add_interface memory_master avalon start
set_interface_property memory_master addressUnits SYMBOLS
set_interface_property memory_master associatedClock avm_clk
set_interface_property memory_master associatedReset avm_reset
set_interface_property memory_master bitsPerSymbol 8
set_interface_property memory_master burstOnBurstBoundariesOnly false
set_interface_property memory_master burstcountUnits WORDS
set_interface_property memory_master doStreamReads false
set_interface_property memory_master doStreamWrites false
set_interface_property memory_master holdTime 0
set_interface_property memory_master linewrapBursts false
set_interface_property memory_master maximumPendingReadTransactions 0
set_interface_property memory_master readLatency 0
set_interface_property memory_master readWaitTime 1
set_interface_property memory_master setupTime 0
set_interface_property memory_master timingUnits Cycles
set_interface_property memory_master writeWaitTime 0
set_interface_property memory_master ENABLED true
set_interface_property memory_master EXPORT_OF ""
set_interface_property memory_master PORT_NAME_MAP ""
set_interface_property memory_master CMSIS_SVD_VARIABLES ""
set_interface_property memory_master SVD_ADDRESS_GROUP ""
add_interface_port memory_master avm_addr address Output 32
add_interface_port memory_master avm_rd read Output 1
add_interface_port memory_master avm_rdvalid readdatavalid Input 1
add_interface_port memory_master avm_rdata readdata Input 16
add_interface_port memory_master avm_wr write Output 1
add_interface_port memory_master avm_wdata writedata Output 16
add_interface_port memory_master avm_wait waitrequest Input 1

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///////////////////////////////////////////////////////
// Module: external bus master for STM32 FSMC //
///////////////////////////////////////////////////////
module ext_master(
addr, ncs, rd_start, wr_start, byte_en, data_in, data_out, wait_out,
avm_clk, avm_reset, avm_addr, avm_rd, avm_rdvalid, avm_rdata, avm_wr, avm_wdata, avm_byte_en, avm_wait
);
///////////////////////////////////////////////////////
// Pins //
///////////////////////////////////////////////////////
// external signal
input[31:0] addr;
input ncs;
input rd_start;
input wr_start;
input[1:0] byte_en;
input[15:0] data_in;
output[15:0] data_out;
output wait_out;
// avalon master
input avm_clk;
input avm_reset;
output[31:0] avm_addr;
output avm_rd;
input[15:0] avm_rdata;
input avm_rdvalid;
output avm_wr;
output[15:0] avm_wdata;
output[1:0] avm_byte_en;
input avm_wait;
///////////////////////////////////////////////////////
// master state //
///////////////////////////////////////////////////////
reg[2:0] mstate;
reg avm_rd;
reg avm_wr;
reg emm_wait;
reg cs_wait;
reg[1:0] avm_byte_en;
reg[15:0] avm_wdata;
reg[31:0] avm_addr;
reg[15:0] data_out;
localparam M_IDLE=0, M_READ=1, M_READ_DATA=2, M_READ_END=3, M_WRITE=4, M_WRITE_END=5;
always @(posedge avm_reset or posedge avm_clk)
begin
if(avm_reset==1) begin
mstate <= M_IDLE;
end else begin
case(mstate)
M_IDLE: begin
if(ncs==0 && rd_start==1) begin
mstate <= M_READ;
avm_rd <= 1;
emm_wait <= 1;
end else if(ncs==0 && wr_start==1) begin
mstate <= M_WRITE;
avm_wr <= 1;
emm_wait <= 1;
end else begin
avm_rd <= 0;
avm_wr <= 0;
emm_wait <= 0;
mstate <= M_IDLE;
end
end
M_READ: begin
if(avm_wait==0) begin
mstate <= M_READ_DATA;
avm_rd <= 0;
end
end
M_READ_DATA: begin
if(avm_rdvalid==1) begin
emm_wait <= 0;
mstate <= M_IDLE;
end
end
M_WRITE: begin
if(avm_wait==0) begin
emm_wait <= 0;
avm_wr <= 0;
mstate <= M_IDLE;
end
end
default: begin
mstate <= M_IDLE;
end
endcase
end
end
always @(posedge emm_wait or negedge ncs)
begin
if(emm_wait==1)
cs_wait <= 0;
else
cs_wait <= 1;
end
always @(posedge avm_clk)
begin
if(avm_rdvalid==1)
data_out <= avm_rdata;
end
always @(posedge avm_clk)
begin
if(ncs==0 && wr_start==1) begin
avm_wdata <= data_in;
avm_byte_en <= byte_en;
end
end
always @(posedge avm_clk)
begin
if(ncs==0 && (wr_start==1 || rd_start==1))
avm_addr <= addr;
end
assign wait_out = ~(cs_wait | emm_wait);
endmodule

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# TCL File Generated by Component Editor 13.1
# Thu Nov 20 11:02:53 CST 2014
# DO NOT MODIFY
#
# ext_master "external bus master" v1.0
# tpu 2014.11.20.11:02:53
#
#
#
# request TCL package from ACDS 13.1
#
package require -exact qsys 13.1
#
# module ext_master
#
set_module_property DESCRIPTION ""
set_module_property NAME ext_master
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP Bridges/Memory-Mapped
set_module_property AUTHOR tpu
set_module_property DISPLAY_NAME "external bus master"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL ext_master
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file ext_master.v VERILOG PATH ext_master.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point avm_clk
#
add_interface avm_clk clock end
set_interface_property avm_clk clockRate 0
set_interface_property avm_clk ENABLED true
set_interface_property avm_clk EXPORT_OF ""
set_interface_property avm_clk PORT_NAME_MAP ""
set_interface_property avm_clk CMSIS_SVD_VARIABLES ""
set_interface_property avm_clk SVD_ADDRESS_GROUP ""
add_interface_port avm_clk avm_clk clk Input 1
#
# connection point avm_reset
#
add_interface avm_reset reset end
set_interface_property avm_reset associatedClock avm_clk
set_interface_property avm_reset synchronousEdges DEASSERT
set_interface_property avm_reset ENABLED true
set_interface_property avm_reset EXPORT_OF ""
set_interface_property avm_reset PORT_NAME_MAP ""
set_interface_property avm_reset CMSIS_SVD_VARIABLES ""
set_interface_property avm_reset SVD_ADDRESS_GROUP ""
add_interface_port avm_reset avm_reset reset Input 1
#
# connection point ext_bus
#
add_interface ext_bus conduit end
set_interface_property ext_bus associatedClock ""
set_interface_property ext_bus associatedReset ""
set_interface_property ext_bus ENABLED true
set_interface_property ext_bus EXPORT_OF ""
set_interface_property ext_bus PORT_NAME_MAP ""
set_interface_property ext_bus CMSIS_SVD_VARIABLES ""
set_interface_property ext_bus SVD_ADDRESS_GROUP ""
add_interface_port ext_bus addr export Input 32
add_interface_port ext_bus ncs export Input 1
add_interface_port ext_bus rd_start export Input 1
add_interface_port ext_bus wr_start export Input 1
add_interface_port ext_bus data_in export Input 16
add_interface_port ext_bus data_out export Output 16
add_interface_port ext_bus wait_out export Output 1
add_interface_port ext_bus byte_en export Input 2
#
# connection point memory_master
#
add_interface memory_master avalon start
set_interface_property memory_master addressUnits SYMBOLS
set_interface_property memory_master associatedClock avm_clk
set_interface_property memory_master associatedReset avm_reset
set_interface_property memory_master bitsPerSymbol 8
set_interface_property memory_master burstOnBurstBoundariesOnly false
set_interface_property memory_master burstcountUnits WORDS
set_interface_property memory_master doStreamReads false
set_interface_property memory_master doStreamWrites false
set_interface_property memory_master holdTime 0
set_interface_property memory_master linewrapBursts false
set_interface_property memory_master maximumPendingReadTransactions 0
set_interface_property memory_master readLatency 0
set_interface_property memory_master readWaitTime 1
set_interface_property memory_master setupTime 0
set_interface_property memory_master timingUnits Cycles
set_interface_property memory_master writeWaitTime 0
set_interface_property memory_master ENABLED true
set_interface_property memory_master EXPORT_OF ""
set_interface_property memory_master PORT_NAME_MAP ""
set_interface_property memory_master CMSIS_SVD_VARIABLES ""
set_interface_property memory_master SVD_ADDRESS_GROUP ""
add_interface_port memory_master avm_addr address Output 32
add_interface_port memory_master avm_rd read Output 1
add_interface_port memory_master avm_rdvalid readdatavalid Input 1
add_interface_port memory_master avm_rdata readdata Input 16
add_interface_port memory_master avm_wr write Output 1
add_interface_port memory_master avm_wdata writedata Output 16
add_interface_port memory_master avm_wait waitrequest Input 1
add_interface_port memory_master avm_byte_en byteenable Output 2

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///////////////////////////////////////////////////////
// Module: external bus master for STM32 FSMC //
///////////////////////////////////////////////////////
module fsmc_master(
addr, ale, ncs, nrd, nwr, data_in, data_out, wait_out,
avm_clk, avm_reset, avm_addr, avm_rd, avm_rdvalid, avm_rdata, avm_wr, avm_wdata, avm_wait
);
///////////////////////////////////////////////////////
// Pins //
///////////////////////////////////////////////////////
// external signal
input[31:0] addr;
input ale;
input ncs;
input nrd;
input nwr;
input[15:0] data_in;
output[15:0] data_out;
output wait_out;
// io master
input avm_clk;
input avm_reset;
output[31:0] avm_addr;
output avm_rd;
input[15:0] avm_rdata;
input avm_rdvalid;
output avm_wr;
output[15:0] avm_wdata;
input avm_wait;
///////////////////////////////////////////////////////
// input sync //
///////////////////////////////////////////////////////
reg ale_s0, ale_s1, ale_s2;
always @(posedge avm_clk)
begin
ale_s0 <= ale;
ale_s1 <= ale_s0;
ale_s2 <= ale_s1;
end
wire rd_start = (ale_s2==0 && ale_s1==1 && ncs==0 && nrd==0);
reg nwr_s0, nwr_s1, nwr_s2;
always @(posedge avm_clk)
begin
nwr_s0 <= nwr;
nwr_s1 <= nwr_s0;
nwr_s2 <= nwr_s1;
end
wire wr_start = (nwr_s2==1 && nwr_s1==0 && ncs==0);
///////////////////////////////////////////////////////
// master read //
///////////////////////////////////////////////////////
reg[2:0] mstate;
reg avm_rd;
reg avm_wr;
reg emm_wait;
reg cs_wait;
reg[15:0] avm_wdata;
reg[31:0] avm_addr;
reg[15:0] data_out;
localparam M_IDLE=0, M_READ=1, M_READ_DATA=2, M_READ_END=3, M_WRITE=4, M_WRITE_END=5;
always @(posedge avm_reset or posedge avm_clk)
begin
if(avm_reset==1) begin
mstate <= M_IDLE;
end else begin
case(mstate)
M_IDLE: begin
if(rd_start==1) begin
mstate <= M_READ;
avm_rd <= 1;
emm_wait <= 1;
end else if(wr_start==1) begin
mstate <= M_WRITE;
avm_wr <= 1;
emm_wait <= 1;
end else begin
avm_rd <= 0;
avm_wr <= 0;
emm_wait <= 0;
mstate <= M_IDLE;
end
end
M_READ: begin
if(avm_wait==0) begin
mstate <= M_READ_DATA;
avm_rd <= 0;
end
end
M_READ_DATA: begin
if(avm_rdvalid==1) begin
emm_wait <= 0;
mstate <= M_IDLE;
end
end
M_WRITE: begin
if(avm_wait==0) begin
emm_wait <= 0;
avm_wr <= 0;
mstate <= M_IDLE;
end
end
default: begin
mstate <= M_IDLE;
end
endcase
end
end
always @(posedge emm_wait or negedge ncs)
begin
if(emm_wait==1)
cs_wait <= 0;
else
cs_wait <= 1;
end
always @(posedge avm_clk)
begin
if(avm_rdvalid==1)
data_out <= avm_rdata;
end
always @(posedge avm_clk)
begin
if(wr_start==1)
avm_wdata <= data_in;
end
always @(posedge avm_clk)
begin
if(wr_start==1 || rd_start==1)
avm_addr <= addr;
end
assign wait_out = ~(cs_wait | emm_wait);
endmodule

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///////////////////////////////////////////////////////
// Module: external bus master for Saturn ABUS //
///////////////////////////////////////////////////////
module saturn_master(
addr, ale, ncs, nrd, nwr, data_in, data_out, wait_out,
avm_clk, avm_reset, avm_addr, avm_rd, avm_rdvalid, avm_rdata, avm_wr, avm_wdata, avm_wait
);
///////////////////////////////////////////////////////
// Pins //
///////////////////////////////////////////////////////
// external signal
input[31:0] addr;
input ale;
input ncs;
input nrd;
input nwr;
input[15:0] data_in;
output[15:0] data_out;
output wait_out;
// io master
input avm_clk;
input avm_reset;
output[31:0] avm_addr;
output avm_rd;
input[15:0] avm_rdata;
input avm_rdvalid;
output avm_wr;
output[15:0] avm_wdata;
input avm_wait;
///////////////////////////////////////////////////////
// input sync //
///////////////////////////////////////////////////////
reg ncs_s0, ncs_s1, ncs_s2, ncs_s3, ncs_s4;
always @(posedge avm_clk)
begin
ncs_s0 <= ncs;
ncs_s1 <= ncs_s0;
ncs_s2 <= ncs_s1;
ncs_s3 <= ncs_s2;
ncs_s4 <= ncs_s3;
end
wire rd_start = (ncs_s2==1 && ncs_s1==0 && nrd==0);
wire wr_start = (ncs_s4==1 && ncs_s3==0 && nwr==0);
///////////////////////////////////////////////////////
// master read //
///////////////////////////////////////////////////////
reg[2:0] mstate;
reg avm_rd;
reg avm_wr;
reg emm_wait;
reg cs_wait;
reg[15:0] avm_wdata;
reg[31:0] avm_addr;
reg[15:0] data_out;
localparam M_IDLE=0, M_READ=1, M_READ_DATA=2, M_READ_END=3, M_WRITE=4, M_WRITE_END=5;
always @(posedge avm_reset or posedge avm_clk)
begin
if(avm_reset==1) begin
mstate <= M_IDLE;
end else begin
case(mstate)
M_IDLE: begin
if(rd_start==1) begin
mstate <= M_READ;
avm_rd <= 1;
emm_wait <= 1;
end else if(wr_start==1) begin
mstate <= M_WRITE;
avm_wr <= 1;
emm_wait <= 1;
end else begin
avm_rd <= 0;
avm_wr <= 0;
emm_wait <= 0;
mstate <= M_IDLE;
end
end
M_READ: begin
if(avm_wait==0) begin
mstate <= M_READ_DATA;
avm_rd <= 0;
end
end
M_READ_DATA: begin
if(avm_rdvalid==1) begin
emm_wait <= 0;
mstate <= M_IDLE;
end
end
M_WRITE: begin
if(avm_wait==0) begin
emm_wait <= 0;
avm_wr <= 0;
mstate <= M_IDLE;
end
end
default: begin
mstate <= M_IDLE;
end
endcase
end
end
always @(posedge emm_wait or negedge ncs)
begin
if(emm_wait==1)
cs_wait <= 0;
else
cs_wait <= 1;
end
always @(posedge avm_clk)
begin
if(avm_rdvalid==1)
data_out <= avm_rdata;
end
always @(posedge avm_clk)
begin
if(wr_start==1)
avm_wdata <= data_in;
end
always @(posedge avm_clk)
begin
if(wr_start==1 || rd_start==1)
avm_addr <= addr;
end
assign wait_out = ~(cs_wait | emm_wait);
endmodule

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FPGA/saturn_master/saturn_master_hw.tcl Normal file
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# TCL File Generated by Component Editor 13.1
# Sat Nov 08 11:20:10 CST 2014
# DO NOT MODIFY
#
# saturn_master "saturn bus master" v1.0
# tpu 2014.11.08.11:20:09
#
#
#
# request TCL package from ACDS 13.1
#
package require -exact qsys 13.1
#
# module saturn_master
#
set_module_property DESCRIPTION ""
set_module_property NAME saturn_master
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP Bridges/Memory-Mapped
set_module_property AUTHOR tpu
set_module_property DISPLAY_NAME "saturn bus master"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL saturn_master
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
add_fileset_file saturn_master.v VERILOG PATH saturn_master.v TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point avm_clk
#
add_interface avm_clk clock end
set_interface_property avm_clk clockRate 0
set_interface_property avm_clk ENABLED true
set_interface_property avm_clk EXPORT_OF ""
set_interface_property avm_clk PORT_NAME_MAP ""
set_interface_property avm_clk CMSIS_SVD_VARIABLES ""
set_interface_property avm_clk SVD_ADDRESS_GROUP ""
add_interface_port avm_clk avm_clk clk Input 1
#
# connection point avm_reset
#
add_interface avm_reset reset end
set_interface_property avm_reset associatedClock avm_clk
set_interface_property avm_reset synchronousEdges DEASSERT
set_interface_property avm_reset ENABLED true
set_interface_property avm_reset EXPORT_OF ""
set_interface_property avm_reset PORT_NAME_MAP ""
set_interface_property avm_reset CMSIS_SVD_VARIABLES ""
set_interface_property avm_reset SVD_ADDRESS_GROUP ""
add_interface_port avm_reset avm_reset reset Input 1
#
# connection point saturn_bus
#
add_interface saturn_bus conduit end
set_interface_property saturn_bus associatedClock ""
set_interface_property saturn_bus associatedReset ""
set_interface_property saturn_bus ENABLED true
set_interface_property saturn_bus EXPORT_OF ""
set_interface_property saturn_bus PORT_NAME_MAP ""
set_interface_property saturn_bus CMSIS_SVD_VARIABLES ""
set_interface_property saturn_bus SVD_ADDRESS_GROUP ""
add_interface_port saturn_bus addr export Input 32
add_interface_port saturn_bus ale export Input 1
add_interface_port saturn_bus ncs export Input 1
add_interface_port saturn_bus nrd export Input 1
add_interface_port saturn_bus nwr export Input 1
add_interface_port saturn_bus data_in export Input 16
add_interface_port saturn_bus data_out export Output 16
add_interface_port saturn_bus wait_out export Output 1
#
# connection point memory_master
#
add_interface memory_master avalon start
set_interface_property memory_master addressUnits SYMBOLS
set_interface_property memory_master associatedClock avm_clk
set_interface_property memory_master associatedReset avm_reset
set_interface_property memory_master bitsPerSymbol 8
set_interface_property memory_master burstOnBurstBoundariesOnly false
set_interface_property memory_master burstcountUnits WORDS
set_interface_property memory_master doStreamReads false
set_interface_property memory_master doStreamWrites false
set_interface_property memory_master holdTime 0
set_interface_property memory_master linewrapBursts false
set_interface_property memory_master maximumPendingReadTransactions 0
set_interface_property memory_master readLatency 0
set_interface_property memory_master readWaitTime 1
set_interface_property memory_master setupTime 0
set_interface_property memory_master timingUnits Cycles
set_interface_property memory_master writeWaitTime 0
set_interface_property memory_master ENABLED true
set_interface_property memory_master EXPORT_OF ""
set_interface_property memory_master PORT_NAME_MAP ""
set_interface_property memory_master CMSIS_SVD_VARIABLES ""
set_interface_property memory_master SVD_ADDRESS_GROUP ""
add_interface_port memory_master avm_addr address Output 32
add_interface_port memory_master avm_rd read Output 1
add_interface_port memory_master avm_rdvalid readdatavalid Input 1
add_interface_port memory_master avm_rdata readdata Input 16
add_interface_port memory_master avm_wr write Output 1
add_interface_port memory_master avm_wdata writedata Output 16
add_interface_port memory_master avm_wait waitrequest Input 1