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Docs: New TODO moved to EMU, old renamed to old_todo Docs: Old coding style is deprecated (old_style.txt) Docs: Removed mention about CubeDocumented and fixed old emails RE: boot.s, proved first asm line (lis instruction parameter) RE: Added PAL and NTSC Boot and IPL IDA files RE: Some work on NTSC IPL (identified many lib calls, including OS, GX) RE: Added EXI Bootrom descrambler by segher RE: GXInit RE: Internal GX lib structures (GXPrivate.h) RE: More details on lomem (OS versions) RE: OSInit and OS.c RE: OSAlloc (heap allocator) RE: Very first code of Metrowerk runtime (__start.c) Docs: Added copy of http://gcdev.narod.ru Source\Utils: Command processor (Cmd.c) Source\Utils: File wrapper Source\Utils: Gekko disasm cleaned up and ported to plain C Source\Utils: Double-linked lists Source\Utils: Ported old Profiler code Source\Utils: String utils
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592 lines
No EOL
33 KiB
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<html>
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<head>
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<style>pre { font-family: Courier; font-size: 8pt;}</style>
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</head>
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<body>
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<center><u><h2>Serial Interface</h2></u></center>
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The base address of interface registers is <b><font face=Verdana color=PURPLE size=2pt>CC006400</font></b>.
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All registers are 32-bit.
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<br><br>
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<b>SI Channel 0 Output Buffer</b>
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<b><font face=Verdana color=PURPLE size=2pt>CC006400</font></b><br>
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<PRE>SIC0OUTBUF :
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Bits Mnemonic Type Reset Description
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31:24 R 0 Reserved
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23:16 CMD RW 0 Command: This byte is the opcode for the command
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sent to the controller during each command/response
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packet. This is the first data byte sent from the SI I/F to
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the game controller in the command/response packet.
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15:8 OUTPUT0 RW 0 Output Byte 0: This is the first data byte of the
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command packet. It is the second data byte sent from
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the SI I/F to the game controller in the
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command/response packet.
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7:0 OUTPUT1 RW 0 Output Byte 1: This is the second databyte of the
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command packet. It is the third data byte sent from the
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SI I/F to the game controller in the command/response packet.
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</PRE>
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This register is double buffered, so main processor writes to the
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SIC0OUTBUF will not interfere with the serial interface output
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transfer. Internally, a second buffer is used to hold the output data to be
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transferred across the serial interface. To check if SIC0OUTBUF
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has been transferred to the second buffer, main processor polls the
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SISR[WRST0] register. When SICOOUTBUF is transferred, SISR[WRST0] is cleared. <br><br>
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<b>SI Channel 0 Input Buffer High</b>
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<b><font face=Verdana color=PURPLE size=2pt>CC006404</font></b><br>
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<PRE>SIC0INBUFH:
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Bits Mnemonic Type Reset Description
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31 ERRSTAT R 0 Error Status: This bit represents the current error status
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for the last SI polling transfer on channel 0. This
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register is updated after each polling transfer on this channel.
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0 = No error on last transfer
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1 = Error on last transfer
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30 ERRLATCH R 0 Error Latch: This bit is an error status summary of the
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SISR error bits for this channel. If an error has
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occurred on a past SI transfer on channel 0 (polling or
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Com transfer), this bit will be set. To determine the
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exact error, read the SISR register. This bit is actually
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an `or` of the latched error status bits for channel 0 in
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the SISR. The bit is cleared by clearing the appropriate
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error status bits latched in the SISR. The no response
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error indicates that a controller is not present on this channel.
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0 = No errors latched
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1 = Error latched. Check SISR.
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29:24 INPUT0 R Input Byte 0: This is the first data byte of the response
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packet sent from the game controller to the SI I/F for
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channel 0. The top two bits of the byte returning from
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the controller are assumed to be `0`, so they are not
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included.
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23:16 INPUT1 R Input Byte 1: This is the second data byte of the
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response packet sent from the game controller to the SI
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I/F for channel 0.
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15:8 INPUT2 R Input Byte 2: This is the third data byte of the response
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packet sent from the game controllers to the SI I/F for
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channel 0.
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7:0 INPUT3 R Input Byte 3: This is the fourth data byte of the
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response packet sent from the game controller to the SI
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I/F for channel 0.
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</PRE>
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SIC0INBUFH and SIC0INBUFL are double buffered to prevent
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inconsistent data reads due to main processor conflicting with incoming
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<B><I>serial</I></B> interface data. To insure data read from SIC0INBUFH and
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SIC0INFUBL are consistent, a locking mechanism prevents the double buffer from
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copying new data to these registers. Once SIC0INBUFH is read, both SIC0INBUFH
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and SIC0INBUFL are `locked` until SIC0INBUFL is read. While the buffers are
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`locked`, new data is not copied into the buffers. When SIC0INBUFL is read, the
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buffers become unlocked again. <BR><BR>SIC0INBUF SI Channel 0 Input Buffer Low
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<BR><BR>Mnemonic: SIC0INBUFL <BR><BR>Offset: 0x08 <BR><BR>Size 32 bits <PRE> SIC0INBUFL
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Bits Mnemonic Type Reset Description
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31:24 INPUT4 R 0 .times. 0 Input Byte 4: See Description of
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SIC1INBUFH[INPUT1].
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23:16 INPUT5 R 0 .times. 0 Input Byte 5: See Description of
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SIC1INBUFH[INPUT1].
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15:8 INPUT6 R 0 .times. 0 Input Byte 6: See Description of
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SIC1INBUFH[INPUT1].
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7:0 INPUT7 R 0 .times. 0 Input Byte 7: See Description of
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SIC1INBUFH[INPUT1].
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</PRE><BR><BR>SIC1OUTBUF SI Channel 1 Output Buffer <BR><BR>Mnemonic: SIC 1
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OUTBUF <BR><BR>Offset: 0x0C <BR><BR>Size 32 bits <PRE> SIC1OUTBUF
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Bits Mnemonic Type Reset Description
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31:24 R 0 .times. 0 Reserved
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23:16 CMD RW 0 .times. 0 Command: For SI channel 1. See
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SIC0OUTBUFF[CMD]
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description.
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15:8 OUTPUT0 RW 0 .times. 0 Output Byte 0: For SI channel 1. See
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SIC0OUTBUFF[OUTPUT0
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description.
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7:0 OUTPUT1 RW 0 .times. 0 Output Byte 1: For SI channel 1. See
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SIC0OUTBUFF[OUTPUT1]
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description.
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</PRE><BR><BR>SIC1INBUF SI Channel 1 Input Buffer High <BR><BR>Mnemonic:
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SIC1INBUFH <BR><BR>Offset: 0x10 <BR><BR>Size 32 bits <PRE> SIC1INBUFH
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Bits Mnemonic Type Reset Description
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31 ERRSTAT R 0 .times. 0 Error Status: See Description of
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SIC0INBUFH[ERRSTAT].
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30 ERRLATCH R 0 .times. 0 Error Latch: See Description of
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SIC0INBUFH[ERRLATCH].
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29:24 INPUT0 R 0 .times. 0 Input Byte 0: See Description of
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SIC0INBUFH[INPUT0].
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23:16 INPUT1 R 0 .times. 0 Input Byte 1: See Description of
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SIC0INBUFH[INPUT1].
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15:8 INPUT2 R 0 .times. 0 Input Byte 2: See Description of
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SIC0INBUFH[INPUT1].
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7:0 INPUT3 R 0 .times. 0 Input Byte 3: See Description of
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SIC0INBUFH[INPUT1].
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</PRE><BR><BR>SIC1INBUF SI Channel 1 Input Buffer Low <BR><BR>Mnemonic:
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SIC1INBUFL <BR><BR>Offset: 0x14 <BR><BR>Size 32 bits <PRE> SIC1INBUFL
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Bits Mnemonic Type Reset Description
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31:24 INPUT4 R 0 .times. 0 Input Byte 4: See Description of
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SIC0INBUFH[INPUT1].
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23:16 INPUT5 R 0 .times. 0 Input Byte 5: See Description of
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SIC0INBUFH[INPUT1].
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15:8 INPUT6 R 0 .times. 0 Input Byte 6: See Description of
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SIC0INBUFH[INPUT1].
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7:0 INPUT7 R 0 .times. 0 Input Byte 7: See Description of
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SIC0INBUFH[INPUT1].
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</PRE><BR><BR>SIC2OUTBUF SI Channel 2 Output Buffer <BR><BR>Mnemonic: SIC2OBUF
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<BR><BR>Offset: 0x18 <BR><BR>Size 32 bits <PRE> SIC2OUTBUF
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Bits Mnemonic Type Reset Description
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31:24 R 0 .times. 0 Reserved
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23:16 CMD RW 0 .times. 0 Command: For SI Channel 2. See
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SIC0OUTBUFF[CMD]
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description
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15:8 OUTPUT0 RW 0 .times. 0 Output Byte 0: For SI channel 2. See
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SIC0OUTBUFF[OUTPUT0]
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description.
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7:0 OUTPUT1 RW 0 .times. 0 Output Byte 1: For SI channel 2. See
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SIC0OUTBUFF[OUTPUT1]
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description.
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</PRE><BR><BR>SIC2INBUF SI Channel 2 Input Buffer High <BR><BR>Mnemonic:
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SIC2INBUFH <BR><BR>Offset: 0x1C <BR><BR>Size 32 bits <PRE> SIC2INBUFH
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Bits Mnemonic Type Reset Description
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31 ERRSTAT R 0 .times. 0 Error Status: See Description of
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SIC0INBUFH[ERRSTAT].
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30 ERRLATCH R 0 .times. 0 Error Latch: See Description of
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SIC0INBUFH[ERRLATCH].
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29:24 INPUT0 R 0 .times. 0 Input Byte O: See Description of
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SIC0INBUFH[INPUT1].
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23:16 INPUT1 R 0 .times. 0 Input Byte 1: See Description of
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SIC0INBUFH[INPUT0].
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15:8 INPUT2 R 0 .times. 0 Input Byte 2: See Description of
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SIC0INBUFH[INPUT1].
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7:0 INPUT3 R 0 .times. 0 Input Byte 3: See Description of
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SIC0INBUFH[INPUT1].
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</PRE><BR><BR>SIC2INBUF SI Channel 2 Input Buffer Low <BR><BR>Mnemonic:
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SIC2INBUFL <BR><BR>Offset: 0x20 <BR><BR>Size 32 bits <PRE> SIC2INBUFL
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Bits Mnemonic Type Reset Description
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31:24 INPUT4 R 0 .times. 0 Input Byte 4: See Description of
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SIC0INBUFH[INPUT0].
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23:16 INPUT5 R 0 .times. 0 Input Byte 5: See Description of
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SIC0INBUFH[INPUT0].
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15:8 INPUT6 R 0 .times. 0 Input Byte 6: See Description of
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SIC0INBUFH[INPUT0].
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7:0 INPUT7 R 0 .times. 0 Input Byte 7: See Description of
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SIC0INBUFH[INPUT0].
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</PRE><BR><BR>SIC30UTBUF SI Channel 3 Output Buffer <BR><BR>Mnemonic: SIC3OBUF
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<BR><BR>Offset: 0x24 <BR><BR>Size 32 bits <PRE> SIC3OUTBUF
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Bits Mnemonic Type Reset Description
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31:24 R 0 .times. 0 Reserved
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23:16 CMD RW 0 .times. 0 Command: For SI channel 3. See
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SIC0OUTBUFF[CMD0]
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description
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15:8 OUTPUT0 RW 0 .times. 0 Output Byte 0: For SI channel 3. See
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SIC0OUTBUFF[OUTPUT0]
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description
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7:0 OUTPUT1 RW 0 .times. 0 Output Byte 1: For SI channel 3. See
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SIC0OUTBUFF[OUTPUT1]
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description
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</PRE><BR><BR>SIC3INBUF SI Channel 3 Input Buffer High <BR><BR>Mnemonic:
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SIC3INBUFH <BR><BR>Offset: 0x28 <BR><BR>Size 32 bits <PRE> SIC3INBUFH
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Bits Mnemonic Type Reset Description
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31 ERRSTAT R 0 .times. 0 Error Status: See Description of
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SIC0INBUFH[ERRSTAT].
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30 ERRLATCH R 0 .times. 0 Error Latch: See Description of
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SIC0INBUFH[ERRLATCH].
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29:24 INPUT0 R 0 .times. 0 Input Byte 0: See Description of
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SIC0INBUFH[INPUT0].
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23:16 INPUT1 R 0 .times. 0 Input Byte 1: See Description of
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SIC0INBUFH[INPUT1].
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15:8 INPUT2 R 0 .times. 0 Input Byte 2: See Description of
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SIC0INBUFH[INPUT1]
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7:0 INPUT3 R 0 .times. 0 Input Byte 3: See Description of
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SIC0INBUFH[INPUT1].
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</PRE><BR><BR>SIC3INBUF SI Channel 3 Input Buffer Low <BR><BR>Mnemonic:
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SIC3INBUFL <BR><BR>Offset: 0x2C <BR><BR>Size 32 bits <PRE> SIC4INBUFL
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Bits Mnemonic Type Reset Description
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31:24 INPUT4 R 0 .times. 0 Input Byte 4: See Description of
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SIC0INBUFH[INPUT1].
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23:16 INPUT5 R 0 .times. 0 Input Byte 5: See Description of
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SIC0INBUFH[INPUT1].
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15:8 INPUT6 R 0 .times. 0 Input Byte 6: See Description of
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SIC0INBUFH[INPUT1].
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7:0 INPUT7 R 0 .times. 0 Input Byte 7: See Description of
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SIC0INBUFH[INPUT1].
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</PRE><BR><BR>SIPOLL SI Poll Register <BR><BR>Mnemonic: SIPOLL <BR><BR>Offset:
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0x30 <BR><BR>Size 32 bits <PRE> SIPOLL
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Bits Mnemonic Type Reset Description
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31:26 R 0 .times. 0 Reserved
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25:16 X RW 0 .times. 07 X lines register: determines the
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number of horizontal
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video lines between polling (the polling
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interval).
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The polling begins at vsync. 0 .times. 07
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is the minimum
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setting (determined by the time required to
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complete
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a single polling of the controller). The
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maximum
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setting depends on the current video mode
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(number of
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lines per vsync) and the SIPOLL[Y]
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register. This
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register takes affect after vsync.
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15:8 Y RW 0 .times. 0 Y times register: This register
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determines the number
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of times the SI controllers are polled in a
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single
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frame. This register takes affect after
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vsync.
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7 EN0 RW 0 .times. 0 Enable channel 0: Enable polling of
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channel 0.
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When the channel is enabled, polling begins
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at the
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next vblank. When the channel is disabled,
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polling is
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stopped immediately after the current
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transaction.
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The status of this bit does not affect
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communication
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RAM transfers on this channel.
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1 = Polling of channel 0 is enabled
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0 = Polling of channel 0 is disabled
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6 EN1 RW 0 .times. 0 Enable channel 1: See description for
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SIPOLL[EN0].
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5 EN2 RW 0 .times. 0 Enable channel 2: See Description for
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SIPOLL[EN0].
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4 EN3 RW 0 .times. 0 Enable channel 3: See Description for
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SIPOLL[EN0].
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3 VBCPY0 RW 0 .times. 0 Vblank copy output channel 0: Normally
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main
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processor writes to the SIC0OUTBUF register
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are
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copied immediately to the channel 0 output
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buffer if a
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transfer is not currently in progress. When
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this bit is
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asserted, main processor writes to channel
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0's
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SIC0OUTBUF will only be copied to the
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outbuffer
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on vblank. This is used to control the
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timing of
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commands to 3D LCD shutter glasses
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connected to
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the VI.
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1 = Copy SIC0OUTBUF to output buffer only
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on
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vblank.
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0 = Copy SIC0OUTBUF to output buffer after
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writing.
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2 VBCPY1 RW 0 .times. 0 Vblank copy output channel 1: See
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Description for
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SIPOLL[VBCPY0].
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1 VBCPY2 RW 0 .times. 0 Vblank copy output channel 2: See
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Description for
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SIPOLL[VBCPY0].
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0 VBCPY3 RW 0 .times. 0 Vblank copy output channel 3: See
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Description for
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SIPOLL[VBCPY0].
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</PRE><BR><BR>SICOMCSR SI Communication Control Status Register
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<BR><BR>Mnemonic: SICOMCSR <BR><BR>Offset: 0x34 <BR><BR>Size 32 bits <PRE> SICOMCSR
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Bits Mnemonic Type Reset Description
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31 TCINT RWC 0 .times. 0 Transfer Complete Interrupt Status
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and clear. On
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read this bit indicates the current
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status of the
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communication transfer complete
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interrupt. When a
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`1` is written to this register, the
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interrupt is cleared.
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Write:
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0 = No effect
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1 = Transfer Complete Interrupt
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Read:
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0 = Transfer Complete Interrupt not
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requested
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1 = Transfer Complete Interrupt has been
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requested
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30 TCINTMSK RW 0 .times. 0 Transfer Complete Interrupt Mask:
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Interrupt masking
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prevents the interrupt from being sent to
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the main
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processor, but does not affect the
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assertion of
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SICOMCSR[TCINT]
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0 = Interrupt masked
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1 = Interrupt enabled
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29 COMERR R 0 .times. 0 Communication Error: This indicates
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whether the
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last SI communication transfer had an
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error. See SiSr
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for the cause of the error.
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0 = No
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1 = Error on transfer
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28 RDSTINT R 0 .times. 0 Read Status Interrupt Status and
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clear. On read this
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bit indicates the current status of the
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Read Status
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interrupt. The interrupt is set whenever
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SISR[RDSTn] bits are set. The interrupt
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is cleared
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when all of the RdSt bits in the SISR are
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cleared by
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reading from the Si Channel Input
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Buffers. This
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interrupt can be used to indicate that a
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polling transfer
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has completed and new data is captured in
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the input
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registers
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Read:
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0 = Transfer Complete Interrupt not
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requested
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1 = Transfer Complete Interrupt has been
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requested
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27 RDSTINTMSK RW 0 .times. 0 Read Status interrupt Mask:
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Interrupt masking
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prevents the interrupt from being sent to
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the main
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processor, but does not affect the
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assertion of
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SICOMCSR[RDSTINT]
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0 = Interrupt masked
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1 = Interrupt enabled
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26:23 R 0 .times. 0 Reserved
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22:16 OUTLNGTH RW 0 .times. 0 Communication Channel Output Length
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in bytes.
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Minimum transfer is 1 byte. A value of 0
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.times. 00 will
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transfer 128 bytes. These bits should not
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be modified
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while SICOM transfer is in progress.
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15 R 0 .times. 0 Reserved
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14:8 INLNGTH RW 0 .times. 0 Communication Channel Output Length
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in bytes.
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Minimum transfer is 1 byte. A value of 0
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.times. 00 will
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transfer 128 bytes. These bits should not
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be modified
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while SICOM transfer is in progress.
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2:1 CHANNEL RW 0 .times. 0 Channel: determines which SI
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channel will be used
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the communication interface.
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00 = Channel 1
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01 = Channel 2
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10 = Channel 3
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11 = Channel 4
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These bits should not be modified while
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SICOM
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transfer is in progress.
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0 TSTART RW 0 .times. 0 Transfer Start: When a `1` is
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written to this register,
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the current communication transfer is
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executed. The
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transfer begins immediately after the
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current
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transaction on this channel has
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completed. When
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read this bit represents the current
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transfer status.
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Once a communication transfer has been
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executed,
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polling will resume at the next vblank if
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the channel's
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SIPOLL[ENn] bit is set.
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Write:
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0 = Do not start command
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1 = Start command
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Read:
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0 = Command Complete
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1 = Command Pending
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</PRE><BR><BR>When programming the SICOMCSR after a SICOM transfers has already
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started (e.g., SICOMCSR[TSTART] is set), the example software reads the current
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value first, then and/or in the proper data and then write the new data back.
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The software should not modify any of the transfer parameters (OUTLNGTH,
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INLNGTH, CHANNEL) until the current transfer is complete. This is done to
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prevent a SICOM transfer already in progress from being disturbed. When writing
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the data back, the software should not set the TSTART bit again unless the
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current transfer is complete and another transfer is required. <BR><BR>SISI SI
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Status Register <BR><BR>Mnemonic: SISR <BR><BR>Offset: 0x38 <BR><BR>Size 32 bits
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<PRE> SISR
|
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Bits Mnemonic Type Reset Description
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31 WR RW 0 .times. 0 Write SICnOUTBUF Register: This
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register controls
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and indicates whether the SICnOUTBUFs have
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been
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copied to the double buffered output buffers.
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This bit
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is cleared after the buffers have been
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copied.
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Write
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1 = Copy all buffers
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0 = No effect
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Read
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1 = Buffer not copied
|
|
0 = Buffer copied
|
|
30 R 0 .times. 0 Reserved
|
|
29 RDST0 R 0 .times. 0 Read Status SIC0OINBUF Register: This
|
|
register
|
|
indicates whether the SIC0INBUFs have been
|
|
captured new data and whether the data has
|
|
already
|
|
been read by the main processor (read
|
|
indicated by
|
|
main processor read of SIC01NBUF[ERRSTAT,
|
|
ERRLATCH, INPUT0, INPUT1)]
|
|
1 = New data available, not read by main
|
|
processor
|
|
0 = No new data available, already read by
|
|
main
|
|
processor
|
|
28 WRST0 R 0 .times. 0 Write Status SIC0OUTBUF Register: This
|
|
register
|
|
indicates whether the SIC0OUTBUFs have been
|
|
copied to the double buffered output buffers.
|
|
This bit
|
|
is cleared after the buffers have been
|
|
copied.
|
|
1 = Buffer not copied
|
|
0 = Buffer copied
|
|
27 NOREP0 RWC 0 .times. 0 No Response Error Channel 0: This
|
|
register indicates
|
|
that a previous transfer resulted in no
|
|
response from
|
|
the controller. This can also be used to
|
|
detect
|
|
whether a controller is connected. If no
|
|
controller is
|
|
connected, this bit will be set. Once set
|
|
this bit
|
|
remains set until it is cleared by the main
|
|
processor.
|
|
To clear this bit write `1` to this register.
|
|
Write:
|
|
0 = No effect
|
|
1 = Clear No Response Error
|
|
Read:
|
|
0 = No Response Error not asserted
|
|
1 = No Response Error asserted
|
|
26 COLL0 RWC 0 .times. 0 Collision Error Channel 0: This
|
|
register indicates
|
|
data collision between controller and main
|
|
unit.
|
|
Once set this bit remains set until it is
|
|
cleared by the
|
|
main processor. To clear this bit write `1`
|
|
to this
|
|
register.
|
|
Write:
|
|
0 = No effect
|
|
1 = Clear Collision Error
|
|
Read:
|
|
0 = Collision Error not asserted
|
|
1 = Collision Error asserted
|
|
25 OVRUN0 RWC 0 .times. 0 Over Run Error Channel 0: This register
|
|
indicates
|
|
that the main unit has received more data
|
|
than
|
|
expected. Once set this bit remains set until
|
|
it is
|
|
cleared by the main processor. To clear this
|
|
bit write
|
|
`1' to this register.
|
|
Write:
|
|
0 = No effect
|
|
1 = Clear Over Run Error
|
|
Read:
|
|
0 = Over Run Error not asserted
|
|
1 = Over Run Error asserted
|
|
24 UNRUN RWC 0 .times. 0 Under Run Error Channel 0: This
|
|
register indicates
|
|
that the main unit has received less data
|
|
than
|
|
expected. Once set this bit remain set until
|
|
it is.
|
|
cleared by the main processor. To clear this
|
|
bit write
|
|
`1` to this register.
|
|
Write:
|
|
0 = No effect
|
|
1 = Clear Under Run Error
|
|
Read:
|
|
0 = Under Run not asserted
|
|
1 = Under Run asserted
|
|
23:22 R 0 .times. 0 Reserved
|
|
21 RDST1 R 0 .times. 0 Read Status SIC1OINBUF Register: See
|
|
SISR[RDST0].
|
|
20 WRST1 R 0 .times. 0 Write Status SIC0OUTBUF Register: See
|
|
SISR[WRST0].
|
|
19 NOREP1 RWC 0 .times. 0 No Response Error Channel 1: See
|
|
SISR[NOREP0].
|
|
18 COLL1 RWC 0 .times. 0 Collision Error Channel 1: See
|
|
SISR[COLL0].
|
|
17 OVRUN1 RWC 0 .times. 0 Over Run Error Channel 1: See
|
|
SISR[OVRUN0].
|
|
16 UNRUN1 RWC 0 .times. 0 Under Run Error Channel 1: See
|
|
SISR[UNRUN0].
|
|
15:14 R 0 .times. 0 Reserved
|
|
13 RDST2 R 0 .times. 0 Read Status SIC1OINBUF Register: See
|
|
SISR[RDST2].
|
|
12 WRST2 R 0 .times. 0 Write Status SIC0OUTBUF Register: See
|
|
SISR[WRST2].
|
|
11 NOREP2 RWC 0 .times. 0 No Response Error Channel 2: See
|
|
SISR[NOREP0].
|
|
10 COLL2 RWC 0 .times. 0 Collision Error Channel 2: See
|
|
SISR[COLL0].
|
|
9 OVRUN2 RWC 0 .times. 0 Over Run Error Channel 2: See
|
|
SISR[OVRUN0].
|
|
8 UNRUN2 RWC 0 .times. 0 Under Run Error Channel 2: See
|
|
SISR[UNRUN0].
|
|
7:6 R 0 .times. 0 Reserved
|
|
5 RDST3 R 0 .times. 0 Read Status SIC1OINBUF Register: See
|
|
SISR[RDST2].
|
|
4 WRST3 R 0 .times. 0 Write Status SIC0OUTBUF Register: See
|
|
SISR[WRST2].
|
|
3 NOREP3 RWC 0 .times. 0 No Response Error Channel 3: See
|
|
SISR[NOREP0].
|
|
2 COLL3 RWC 0 .times. 0 Collision Error Channel 3: See
|
|
SISR[COLL0].
|
|
1 OVRUN3 RWC 0 .times. 0 Over Run Error Channel 3: See
|
|
SISR[OVRUN0].
|
|
0 UNRUN3 RWC 0 .times. 0 Under Run Error Channel 3: See
|
|
SISR[UNRUN0].
|
|
</PRE><BR><BR>SIEXILK SI EXI Clock Lock <BR><BR>Mnemonic: SIEXILK
|
|
<BR><BR>Offset: Ox3C <BR><BR>Size 32 bits <PRE> SIEXILK
|
|
Bits Mnemonic Type Reset Description
|
|
31 LOCK RW 0 .times. 1 Lock: This bit prevents the main
|
|
processor from setting the EXI clock
|
|
frequencies to 32 MHz.
|
|
0 = EXI Clocks Unlocked, 32 MHz
|
|
EXICLK setting permitted.
|
|
1 = EXI Clock Locked, 32 MHz
|
|
EXICLK setting not permitted.
|
|
30:0 R 0 .times. 0 Reserved
|
|
</PRE><BR><BR>FIG. 8D is an even more detailed overall view of
|
|
<B><I>serial</I></B> interface 1000 showing the details of <B><I>serial</I></B>
|
|
interface communication circuitry and registers 1012. Controllers 52a and 52b
|
|
(and 52c and 52d, if present) are connected to game console 54 via connector
|
|
ports 1002. Modem 1404 modulates and demodulates data transferred between the
|
|
controllers and the console. In the example system, communication between the
|
|
console and the controllers uses duty-cycle (pulse-width) modulation and the
|
|
data is communicated over one line. The communication is half-duplex. The byte
|
|
transfer order is "big-endian" in which within a given multi-byte numeric
|
|
representation, the most significant byte has the lowest address (i.e., the data
|
|
is transferred "big-end" first). Controller input/output buffer 1016 is used for
|
|
normal data transfers involving controllers 52a-52d. As shown in FIG. 8D,
|
|
input/output buffer 1016 is arranged as a double buffer. Communication RAM 1014
|
|
is provided for use in variable-size data transfers to and from controllers
|
|
52a-52d. In the example system, the maximum data size of these variable-size
|
|
data transfers is 32 words. Of course, the present invention is not limited in
|
|
this respect. Channel selector circuit 1408 controls selectors 1412a-1412d to
|
|
selectively connect modem 1404 to either communication RAM 1014 or input/output
|
|
buffer 1016. An HV counter latch circuit 1406 latches the screen position of a
|
|
flash signal when a trigger input is received from a light gun unit. In the
|
|
example system shown in FIG. 8, triggers inputs to the HV counter latch circuit
|
|
1406 are provided for connectors 1 and 2 only. It will be apparent that trigger
|
|
inputs may be provided for the other connectors if desired. HV counter latch
|
|
circuit 1406 may also be used with light pens connected to connectors 1 and/or
|
|
2. <BR><BR>Additional details of the <B><I>serial</I></B> interface may be found
|
|
in application Ser. No. 09/722,664 filed Nov. 28, 2000 of Shimuzu et al.
|
|
entitled "Controller Interface for a Graphics System", the contents of which are
|
|
incorporated herein. <BR>
|
|
|
|
<br><hr>
|
|
<br><i>
|
|
Cut from USPTO #6609977<br>
|
|
<a href="mailto:ogamespec@gmail.com">org - ogamespec@gmail.com</a></i>
|
|
</body>
|
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