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c21147ccff
Docs: New TODO moved to EMU, old renamed to old_todo Docs: Old coding style is deprecated (old_style.txt) Docs: Removed mention about CubeDocumented and fixed old emails RE: boot.s, proved first asm line (lis instruction parameter) RE: Added PAL and NTSC Boot and IPL IDA files RE: Some work on NTSC IPL (identified many lib calls, including OS, GX) RE: Added EXI Bootrom descrambler by segher RE: GXInit RE: Internal GX lib structures (GXPrivate.h) RE: More details on lomem (OS versions) RE: OSInit and OS.c RE: OSAlloc (heap allocator) RE: Very first code of Metrowerk runtime (__start.c) Docs: Added copy of http://gcdev.narod.ru Source\Utils: Command processor (Cmd.c) Source\Utils: File wrapper Source\Utils: Gekko disasm cleaned up and ported to plain C Source\Utils: Double-linked lists Source\Utils: Ported old Profiler code Source\Utils: String utils
358 lines
9.1 KiB
Text
358 lines
9.1 KiB
Text
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Exploring of Gekko Special Purpose Registers.
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Version 1.0. (22 Sep 2006)
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------------------------------------------------------------------------------
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SPR 0
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-----
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"mtspr/mfspr is supervisor-only if SPR[0] = 1" as written in PPC manual.
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Set program exception handler.
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In supervisor mode:
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Read SPR[0]: Program Exception (Illegal)
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Write SPR[0] 0x00000001: Program Exception (Illegal)
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Write SPR[0] 0x00000000: Program Exception (Illegal)
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Set MSR[PR] to 1 (user mode)
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Read SPR[0]: Program Exception (Illegal)
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Write SPR[0]: Program Exception (Illegal)
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XER (1)
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-------
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Write 0xFFFFFFFF to XER.
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Result: 0xE000FF7F.
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Second write 0x00000000.
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Result: 0x00000000.
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Bits 16-23 are R/W and probably have some meaning on other PPC models.
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Bits 3-15, 24 are Read 0 only.
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Same for OEA.
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SPR 2, 3, 4, 5, 6, 7
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--------------------
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OEA and UISA Read or Write: Program Exception (Illegal).
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LR (8)
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------
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All bits are valid R/W without any doubts. :)
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Prove:
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mfspr r31, LR
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li r30, 0xFFFF # LR = 0xFFFFFFFF
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mtspr LR, r30
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mfspr r30, LR
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mtspr LR, r31
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mr r3, r30
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bl PrintValue
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Output: 0xFFFFFFFF
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Same for OEA.
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CTR (9)
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-------
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Write: 0xDEADBEEF
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Readed: 0xDEADBEEF
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All bits are R/W.
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Same for OEA.
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SPR 10, 11, 12, 13, 14, 15, 16, 17
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----------------------------------
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OEA and UISA Read or Write: Program Exception (Illegal).
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DSISR (18)
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----------
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OEA: All bits are valid for R/W.
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UISA Read or Write: Program Exception (Privileged).
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DAR (19)
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--------
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OEA: All bits are valid for R/W.
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UISA Read or Write: Program Exception (Privileged).
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SPR 20, 21
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----------
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OEA and UISA Read or Write: Program Exception (Illegal).
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DEC (22)
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--------
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OEA: All bits are valid for R/W.
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UISA Read or Write: Program Exception (Privileged).
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Countering down :)
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SPR 23, 24
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----------
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OEA and UISA Read or Write: Program Exception (Illegal).
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SDR1 (25)
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---------
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OEA:
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Write 0xFFFFFFFF. Read result: 0xFFFF01FF. Bits 16-22 are read-only zero.
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UISA: Read or Write: Program Exception (Privileged).
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SRR0 (26)
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---------
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OEA:
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Write 0xFFFFFFFF. Read result: 0xFFFFFFFF. All bits are valid for R/W, but
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official manual says bits 30-31 are reserved.
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UISA: Read or Write: Program Exception (Privileged).
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SRR1 (27)
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---------
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OEA:
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Write 0xFFFFFFFF. Read result: 0xFFFFFFFF. All bits are valid for R/W.
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UISA: Read or Write: Program Exception (Privileged).
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SPRG0-SPRG3 (272-275)
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---------------------
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OEA:
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Write value 0xFFFFFFFF to any registers.
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Readed: 0xFFFFFFFF.
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Write SPRG0 0xAAAAAAAA;
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Write SPRG1 0xBBBBBBBB;
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Write SPRG2 0xCCCCCCCC;
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Write SPRG3 0xDDDDDDDD;
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Results are:
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SPRG0 0xAAAAAAAA;
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SPRG1 0xBBBBBBBB;
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SPRG2 0xCCCCCCCC;
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SPRG3 0xDDDDDDDD;
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All bits are valid for R/W.
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UISA: Read or Write: Program Exception (Privileged).
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SPR 276-281
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-----------
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OEA and UISA Read or Write: Program Exception (Illegal).
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EAR (282)
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---------
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OEA:
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Write 0xFFFFFFFF.
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Readed: 0x8000000F. Bits 1-25 are read 0 only.
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UISA Read and Write: Program Exception (Privileged).
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SPR 283
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-------
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OEA and UISA Read or Write: Program Exception (Illegal).
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TBL and TBU (284 and 285)
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-------------------------
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OEA:
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Read TBL and TBU via mfspr, and read TBL and TBU via mftb:
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SPR 285: 0x00000000 TBU: 0x00000000
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SPR 284: 0x48F4202F TBL: 0x48F429DD (small time need for read)
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Write 0xAABBCCDD to SPR 285, and 0x88888888 to SPR 284, results are:
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SPR 285: 0xAABBCCDD TBU: 0xAABBCCDD
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SPR 284: 0x888894E9 TBL: 0x88889ECD (small time need for read)
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All bits are valid for R/W.
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UISA any Read or Write: Program Exception (Privileged).
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SPR 286
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-------
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OEA and UISA Read or Write: Program Exception (Illegal).
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PVR (287)
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---------
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OEA:
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Write 0xFFFFFFFF;
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Readed: 0x00083214. Register is read-only.
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UISA Read and Write: Program Exception (Privileged).
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IBAT0-IBAT3, DBAT0-DBAT3 (528-543)
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----------------------------------
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For IBAT testing I used IBAT3, for DBAT testing I used DBAT3. I'm pretty sure
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other registers work the same, because otherwise PPC UNIX-based software
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never existed :)
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Setting mode OEA:
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Write 0xFFFFFFFF to IBAT3U and IBAT3L. Readed:
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IBAT3U: 0xFFFE1FFF. Bits 15-18 are read 0 only.
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IBAT3L: 0xFFFE007B. Bits 15-24 and 29 are read only. Setting W and G bits
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in WIMG bit-field is allowed (but speciefed by architecture as boundedly-undefined).
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Write 0xFFFFFFFF to DBAT3U and DBAT3L. Readed:
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DBAT3U: 0xFFFE1FFF. Bits 15-18 are read 0 only.
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DBAT3L: 0xFFFE007B. Bits 15-24 and 29 are read only. Setting W and G bits allowed.
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UISA: Attempt to Read or Write cause Program Exception (Privileged).
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GQR0-GQR7 (912-919)
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-------------------
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Write value 0xFFFFFFFF to any registers.
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Readed: 0xFFFFFFFF. All bits are valid R/W.
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Write GQR0 0x11111111;
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Write GQR1 0x22222222;
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Write GQR2 0x33333333;
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Write GQR3 0x44444444;
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Write GQR4 0x55555555;
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Write GQR5 0x66666666;
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Write GQR6 0x77777777;
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Write GQR7 0x88888888;
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Results are:
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GQR0 0x11111111;
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GQR1 0x22222222;
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GQR2 0x33333333;
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GQR3 0x44444444;
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GQR4 0x55555555;
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GQR5 0x66666666;
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GQR6 0x77777777;
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GQR7 0x88888888;
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UISA Read or Write: Program Exception (Privileged).
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HID2 (920)
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----------
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OEA:
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Write 0xFFFFFFFF to HID2.
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Result: 0xF00FFFFF. Sticky bits 8-11 are cannot be written as '1'. You can
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only clear them, when they set by hardware. Bits 4-7 are read only.
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UISA: Set MSR[PR] to 1 (user mode), set program exception handler,
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Read HID2: Program Exception (Privileged)
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Write HID2: Program Exception (Privileged)
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WPAR (921)
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----------
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OEA: Write 0xFFFFFFFF, readed: 0xFFFFFFE0, bits 27-30 are read 0 only. Bit 31
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is read only (set when WGPipe is not empty).
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When running in UISA: Read or Write attempt Program Exception (Privileged).
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DMA_U (922)
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-----------
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OEA: Write 0xFFFFFFFF, readed 0xFFFFFFFF. All bits valid for R/W.
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UISA: Program Exception (Privileged).
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DMA_L (923)
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-----------
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OEA: Write 0xFFFFFFFF, readed 0xFFFFFFFC. Bit 30 is sticky (can write only 1,
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but not 0), when read it shows DMA command status. Bit 31 is sticky (can write
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only 1, but not 0), when read it shows DMA operation. Other bits are R/W.
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UISA: Program Exception (Privileged).
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UMMCR0, UPMC1, UPMC2, USIA, UMMCR1, UPMC3, UPMC4, USDA (936-943)
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----------------------------------------------------------------
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OEA: Attempt to Write cause to Program Exception (Illegal).
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Read is work.
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UISA: Attempt to Write cause to Program Exception (Illegal).
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Read is work.
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SPR 944-951
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-----------
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OEA and UISA Read or Write: Program Exception (Illegal).
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MMCR0, PMC1, PMC2, SIA, MMCR1, PMC3, PMC4, SDA (952-959 respectively)
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---------------------------------------------------------------------
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OEA: Writing 0xFFFFFFFF to any PMC registers, returns 0xFFFFFFFF (all
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bits are valid for R/W) for all registers, except:
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MMCR1: readed value is 0xFFC00000 (bits 10-31 are read 0 only).
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SDA: readed value is 0x00000000 (register is read only).
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UISA: Attempt to Read or Write cause to Program Exception (Privileged).
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HID0 (1008)
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-----------
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OEA:
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Setting some bits may be dangerous, but... :)
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Write: 0xFFFFC3FF (I do not set DCFI, ICFI, DLOCK and ILOCK), Readed:
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same value 0xFFFFC3FF, so all bits are valid R/W. No read only bits.
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UISA: Attempt to Read or Write cause to Program Exception (Privileged).
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HID1 (1009)
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-----------
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OEA:
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Write value 0xFFFFFFFF, readed: 0x80000000 (all bits are read-only), Gekko
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PLL_CFG = 0b1000.
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UISA: Attempt to Read or Write cause to Program Exception (Privileged).
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IABR (1010)
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-----------
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OEA:
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Write 0xFFFFFFFF to IABR, readed value: 0xFFFFFFFE. You cannot set bit 31 !
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Its always 0.
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UISA Read or Write: Program Exception (Privileged).
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SPR 1011, 1012
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--------------
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OEA and UISA Read or Write: Program Exception (Illegal).
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DABR (1013)
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-----------
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OEA:
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Write 0xFFFFFFFF to DABR, readed value: 0xFFFFFFFF.
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UISA Read or Write: Program Exception (Privileged).
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SPR 1014, 1015, 1016
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--------------------
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OEA and UISA Read or Write: Program Exception (Illegal).
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L2CR (1017)
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-----------
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OEA: Write value 0xFFFFFFFF, readed: 0xFFFFFF00. Bits 24-30 are read-only 0.
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Bit 31 is 1 only when global invalidation in progress.
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UISA Read or Write: Program Exception (Privileged).
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SPR 1018
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--------
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OEA and UISA Read or Write: Program Exception (Illegal).
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ICTC (1019)
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-----------
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OEA: Write 0xFFFFFFFF, readed: 0x000001FF. Bits 0-22 are read 0 always.
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UISA: Program Exception (Privileged).
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THRM1 (1020)
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------------
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OEA Write 0xFFFFFFFF.
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Read result is: 0x3F800007. Bits 0-1 are read-only. Bits 9-28 are readed as 0.
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UISA Read or Write: Program Exception (Privileged)
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THRM2 (1021)
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------------
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OEA Write 0xFFFFFFFF.
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Read result is: 0x3F800007. Bits 0-1 are read-only. Bits 9-28 are readed as 0.
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UISA Read or Write: Program Exception (Privileged)
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THRM3 (1022)
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------------
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OEA Write 0xFFFFFFFF.
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Now read, result is: 0xFE003FFF. Bits 7-17 are readed as zero.
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UISA Read or Write: Program Exception (Privileged)
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PIR (1023)
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----------
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This register is defined by PPC architecutre, but should not present in Gekko.
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Lets check:
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OEA and UISA Read or Write: Program Exception (Illegal)
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