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https://github.com/emu-russia/pureikyubu.git
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123 lines
5.8 KiB
C
123 lines
5.8 KiB
C
#pragma once
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// VI registers (can be accessed from any offset and by any size, 1, 2 or 4 bytes)
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#define VI_VERT_TIMING 0x0C002000 // Vertical Timing Register
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#define VI_DISP_CR 0x0C002002 // Display Configuration Register
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#define VI_HORZ_TIMING0 0x0C002004 // Horizontal Timing 0 Register
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#define VI_HORZ_TIMING1 0x0C002008 // Horizontal Timing 1 Register
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#define VI_VERT_TIMING_ODD 0x0C00200C // Odd Field Vertical Timing Register
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#define VI_VERT_TIMING_EVEN 0x0C002010 // Even Field Vertical Timing Register
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#define VI_BBINT_ODD 0x0C002014 // Odd Field Burst Blanking Interval Register
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#define VI_BBINT_EVEN 0x0C002018 // Even Field Burst Blanking Interval Register
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#define VI_TFBL 0x0C00201C // Top Field Base Register L
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#define VI_TFBR 0x0C002020 // Top Field Base Register R
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#define VI_BFBL 0x0C002024 // Bottom Field Base Register L
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#define VI_BFBR 0x0C002028 // Bottom Field Base Register R
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#define VI_DISP_POS 0x0C00202C // Display Position Register
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#define VI_INT0 0x0C002030 // Display Interrupt Register 0
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#define VI_INT1 0x0C002034 // Display Interrupt Register 1
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#define VI_INT2 0x0C002038 // Display Interrupt Register 2
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#define VI_INT3 0x0C00203C // Display Interrupt Register 3
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// ... unknown gap [32 * 3]
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#define VI_TAP0 0x0C00204C // Filter Coefficient Table 0
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#define VI_TAP1 0x0C002050 // Filter Coefficient Table 1
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#define VI_TAP2 0x0C002054 // Filter Coefficient Table 2
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#define VI_TAP3 0x0C002058 // Filter Coefficient Table 3
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#define VI_TAP4 0x0C00205C // Filter Coefficient Table 4
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#define VI_TAP5 0x0C002060 // Filter Coefficient Table 5
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#define VI_TAP6 0x0C002064 // Filter Coefficient Table 6
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// ... unknown gap [32]
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#define VI_CLK_SEL 0x0C00206C // VI Clock Select Register
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#define VI_DTV 0x0C00206E // VI DTV Status Register
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// ... unknown gap [16]
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#define VI_BRDR_HBE 0x0C002072 // Border HBE
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#define VI_BRDR_HBS 0x0C002074 // Border HBS
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// mapping is unknown for regs :
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#define VI_PICT_CR 0 // [16] Picture Configuration Register
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#define VI_DISP_LATCH0 0 // [32] Display Latch Register 0
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#define VI_DISP_LATCH1 0 // [32] Display Latch Register 1
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#define VI_OUT_POL 0 // [8?] Output Polarity Register
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#define VI_HORZ_SCALE 0 // [16] Horizontal Scale Register
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#define VI_SCALE_WIDTH 0 // [16] Scaling Width Register
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// Display Configuration Register mask (for 16-bit register)
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#define VI_CR_ENB 0x0001 // enable the video timing generation
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#define VI_CR_RST 0x0002 // puts VI into its idle state
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#define VI_CR_NIN 0x0004 // 0: interlace, 1: non-interlace
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#define VI_CR_DLR 0x0008 // this bit selects the 3D display mode
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#define VI_CR_LE0(r) ((r>>4)&3) // gun trigger mode
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#define VI_CR_LE1(r) ((r>>6)&3) // to enable Display Latch Register 1
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#define VI_CR_FMT(r) ((r>>8)&3) // indicates current video format
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// Display Position Register mask (for 32-bit register)
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#define VI_POS_VCT(r) ((r>>16)&0x7ff) // vertical count (1...vcount in emu)
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#define VI_POS_HCT(r) (r & 0x7ff) // horizontal count (always 1 in emu)
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// Display Interrupt Register mask (for 32-bit register)
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#define VI_INT_INT 0x80000000 // interrupt status. "1" indicates that an interrupt is active
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#define VI_INT_ENB 0x10000000 // interrupt is enabled if this bit is set
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#define VI_INT_VCT(r) ((r>>16)&0x7ff) // vertical count to generate interrupt
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#define VI_INT_HCT(r) (r & 0x7ff) // horizontal count to generate interrupt (ignored in emu)
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// video modes
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#define VI_NTSC_LIKE 0
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#define VI_PAL_LIKE 1
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// max vertical line count
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#define VI_NTSC_INTER 525 // 60 Hz
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#define VI_NTSC_NON_INTER 263 // 30 Hz
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#define VI_PAL_INTER 625 // 50 Hz
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#define VI_PAL_NON_INTER 313 // 25 Hz
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// ---------------------------------------------------------------------------
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// hardware API
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#pragma pack(push, 1)
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struct RGB
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{
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uint8_t Blue;
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uint8_t Green;
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uint8_t Red;
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uint8_t Reserved;
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};
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#pragma pack(pop)
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// VI state (registers and other data)
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struct VIControl
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{
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volatile uint16_t disp_cr; // display configuration register
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volatile uint32_t tfbl; // video buffer (top field)
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volatile uint32_t bfbl; // video buffer (bottom field)
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volatile uint32_t pos; // beam position
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volatile uint32_t int0; // INT0 status
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volatile uint32_t mode; // see VI modes
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bool inter; // 1, if interlace
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volatile uint32_t vcount; // number of lines for single frame
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int64_t vtime; // frame timer
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int64_t one_frame; // frame length in CPU timer ticks
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bool xfb; // enable video frame buffer (GDI)
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uint8_t* xfbbuf; // translated TFBL pointer
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RGB* gfxbuf; // DIB
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bool log; // do debugger log output
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size_t frames; // frames rendered by VI/GX
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int64_t one_second; // one CPU second in timer ticks
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int videoEncoderFuse;
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};
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extern VIControl vi;
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void VIUpdate();
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void VIStats();
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void VIOpen(HWConfig* config);
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void VIClose();
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void VISetEncoderFuse(int value);
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