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https://github.com/emu-russia/pureikyubu.git
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431 lines
10 KiB
C++
431 lines
10 KiB
C++
// Command Processor registers definitions
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#pragma once
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namespace GX
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{
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// CP Registers (from CPU side). 16-bit access
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enum class CPMappedRegister
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{
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CP_STATUS_ID = 0x00,
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CP_ENABLE_ID = 0x01,
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CP_CLR_ID = 0x02,
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CP_MEMPERF_SEL_ID = 0x03,
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CP_STM_LOW_ID = 0x05,
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CP_FIFO_BASEL_ID = 0x10,
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CP_FIFO_BASEH_ID = 0x11,
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CP_FIFO_TOPL_ID = 0x12,
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CP_FIFO_TOPH_ID = 0x13,
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CP_FIFO_HICNTL_ID = 0x14,
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CP_FIFO_HICNTH_ID = 0x15,
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CP_FIFO_LOCNTL_ID = 0x16,
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CP_FIFO_LOCNTH_ID = 0x17,
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CP_FIFO_COUNTL_ID = 0x18,
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CP_FIFO_COUNTH_ID = 0x19,
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CP_FIFO_WPTRL_ID = 0x1a,
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CP_FIFO_WPTRH_ID = 0x1b,
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CP_FIFO_RPTRL_ID = 0x1c,
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CP_FIFO_RPTRH_ID = 0x1d,
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CP_FIFO_BRKL_ID = 0x1e,
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CP_FIFO_BRKH_ID = 0x1f,
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CP_COUNTER0L_ID = 0x20,
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CP_COUNTER0H_ID = 0x21,
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CP_COUNTER1L_ID = 0x22,
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CP_COUNTER1H_ID = 0x23,
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CP_COUNTER2L_ID = 0x24,
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CP_COUNTER2H_ID = 0x25,
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CP_COUNTER3L_ID = 0x26,
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CP_COUNTER3H_ID = 0x27,
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CP_VC_CHKCNTL_ID = 0x28,
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CP_VC_CHKCNTH_ID = 0x29,
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CP_VC_MISSL_ID = 0x2a,
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CP_VC_MISSH_ID = 0x2b,
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CP_VC_STALLL_ID = 0x2c,
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CP_VC_STALLH_ID = 0x2d,
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CP_FRCLK_CNTL_ID = 0x2e,
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CP_FRCLK_CNTH_ID = 0x2f,
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CP_XF_ADDR_ID = 0x30,
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CP_XF_DATAL_ID = 0x31,
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CP_XF_DATAH_ID = 0x32,
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};
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// CP STATUS register mask layout
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#define CP_SR_OVF (1 << 0) // FIFO overflow (fifo_count > FIFO_HICNT)
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#define CP_SR_UVF (1 << 1) // FIFO underflow (fifo_count < FIFO_LOCNT)
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#define CP_SR_RD_IDLE (1 << 2) // FIFO read unit idle
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#define CP_SR_CMD_IDLE (1 << 3) // CP idle
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#define CP_SR_BPINT (1 << 4) // FIFO reach break point (cleared by disable FIFO break point)
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// CP ENABLE register mask layout
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#define CP_CR_RDEN (1 << 0) // Enable FIFO reads, reset value is 0 disable
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#define CP_CR_BPEN (1 << 1) // FIFO break point enable bit, reset value is 0 disable. Write 0 to clear BPINT
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#define CP_CR_OVFEN (1 << 2) // FIFO overflow interrupt enable, reset value is 0 disable
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#define CP_CR_UVFEN (1 << 3) // FIFO underflow interrupt enable, reset value is 0 disable
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#define CP_CR_WPINC (1 << 4) // FIFO write pointer increment enable, reset value is 1 enable
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#define CP_CR_BPINTEN (1 << 5) // FIFO break point interrupt enable, reset value is 0 disable
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// CP clear register mask layout
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#define CP_CLR_OVFCLR (1 << 0) // clear FIFO overflow interrupt
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#define CP_CLR_UVFCLR (1 << 1) // clear FIFO underflow interrupt
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#pragma pack(push, 8)
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// CPU CP registers
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struct CPHostRegs
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{
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uint16_t sr; // status
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uint16_t cr; // control
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union
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{
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struct
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{
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uint16_t basel;
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uint16_t baseh;
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};
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volatile uint32_t base;
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};
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union
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{
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struct
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{
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uint16_t topl;
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uint16_t toph;
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};
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volatile uint32_t top;
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};
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union
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{
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struct
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{
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uint16_t lomarkl;
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uint16_t lomarkh;
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};
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volatile uint32_t lomark;
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};
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union
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{
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struct
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{
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uint16_t himarkl;
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uint16_t himarkh;
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};
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volatile uint32_t himark;
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};
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union
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{
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struct
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{
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uint16_t cntl;
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uint16_t cnth;
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};
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volatile uint32_t cnt;
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};
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union
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{
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struct
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{
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uint16_t wrptrl;
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uint16_t wrptrh;
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};
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volatile uint32_t wrptr;
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};
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union
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{
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struct
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{
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uint16_t rdptrl;
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uint16_t rdptrh;
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};
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volatile uint32_t rdptr;
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};
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union
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{
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struct
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{
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uint16_t bpptrl;
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uint16_t bpptrh;
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};
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volatile uint32_t bpptr;
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};
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};
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#pragma pack(pop)
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// CP Registers (from GX side). These registers are available only for writing, with the CP_LoadRegs command
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enum class CPRegister
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{
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CP_VC_STAT_RESET_ID = 0x00,
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CP_STAT_ENABLE_ID = 0x10,
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CP_STAT_SEL_ID = 0x20,
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CP_MATINDEX_A_ID = 0x30, // MatrixIndexA 0011xxxx
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CP_MATINDEX_B_ID = 0x40, // MatrixIndexB 0100xxxx
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CP_VCD_LO_ID = 0x50, // VCD_Lo 0101xxxx
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CP_VCD_HI_ID = 0x60, // VCD_Hi 0110xxxx
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CP_VAT_A_ID = 0x70, // VAT_group0 0111x,vat[2:0]
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CP_VAT_B_ID = 0x80, // VAT_group1 1000x,vat[2:0]
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CP_VAT_C_ID = 0x90, // VAT_group2 1001x,vat[2:0]
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CP_ARRAY_BASE_ID = 0xa0, // ArrayBase 1001,array[3:0]
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CP_ARRAY_STRIDE_ID = 0xb0, // ArrayStride 1011,array[3:0]
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};
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// Vertex attributes.
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// Specifies the sequence of attributes in the raw vertex data. Which of the attributes are present is selected by the VCD settings.
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enum class VertexAttr
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{
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VTX_POSMATIDX = 0, // Position/Normal Matrix Index
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VTX_TEX0MTXIDX, // Texture Coordinate 0 Matrix Index
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VTX_TEX1MTXIDX, // Texture Coordinate 1 Matrix Index
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VTX_TEX2MTXIDX, // Texture Coordinate 2 Matrix Index
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VTX_TEX3MTXIDX, // Texture Coordinate 3 Matrix Index
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VTX_TEX4MTXIDX, // Texture Coordinate 4 Matrix Index
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VTX_TEX5MTXIDX, // Texture Coordinate 5 Matrix Index
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VTX_TEX6MTXIDX, // Texture Coordinate 6 Matrix Index
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VTX_TEX7MTXIDX, // Texture Coordinate 7 Matrix Index
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VTX_POS, // Position
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VTX_NRM, // Normal or Normal/Binormal/Tangent
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VTX_COLOR0, // Color 0
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VTX_COLOR1, // Color 1
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VTX_TEXCOORD0, // Texture Coordinate 0
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VTX_TEXCOORD1, // Texture Coordinate 1
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VTX_TEXCOORD2, // Texture Coordinate 2
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VTX_TEXCOORD3, // Texture Coordinate 3
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VTX_TEXCOORD4, // Texture Coordinate 4
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VTX_TEXCOORD5, // Texture Coordinate 5
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VTX_TEXCOORD6, // Texture Coordinate 6
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VTX_TEXCOORD7, // Texture Coordinate 7
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VTX_MAX_ATTR
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};
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// Attribute types (from VCD register)
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enum class AttrType
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{
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VCD_NONE = 0, // attribute stage disabled
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VCD_DIRECT, // direct data
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VCD_INDEX8, // 8-bit indexed data
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VCD_INDEX16 // 16-bit indexed data
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};
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// Vertex Components Count (from VAT register)
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enum class VatCount
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{
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VCNT_POS_XY = 0, // two (x,y)
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VCNT_POS_XYZ = 1, // three (x,y,z)
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VCNT_NRM_XYZ = 0, // three normals
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VCNT_NRM_NBT = 1, // nine normals
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VCNT_CLR_RGB = 0, // three (r,g,b)
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VCNT_CLR_RGBA = 1, // four (r,g,b,a)
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VCNT_TEX_S = 0, // one (s)
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VCNT_TEX_ST = 1 // two (s,t)
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};
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// Vertex Component Format (from VAT register)
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enum class VatFormat
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{
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// For Components (normal, coords)
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VFMT_U8 = 0, // ubyte
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VFMT_S8 = 1, // byte
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VFMT_U16 = 2, // ushort
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VFMT_S16 = 3, // short
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VFMT_F32 = 4, // float
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// For Colors
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VFMT_RGB565 = 0, // 16 bit 565 (three comp)
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VFMT_RGB8 = 1, // 24 bit 888 (three comp)
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VFMT_RGBX8 = 2, // 32 bit 888x (three comp)
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VFMT_RGBA4 = 3, // 16 bit 4444 (four comp)
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VFMT_RGBA6 = 4, // 24 bit 6666 (four comp)
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VFMT_RGBA8 = 5 // 32 bit 8888 (four comp)
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};
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#pragma pack(push, 1)
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union MatrixIndexA
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{
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struct
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{
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int PosNrmIndex : 6;
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int Tex0Index : 6;
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int Tex1Index : 6;
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int Tex2Index : 6;
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int Tex3Index : 6;
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};
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uint32_t bits;
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};
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union MatrixIndexB
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{
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struct
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{
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int Tex4Index : 6;
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int Tex5Index : 6;
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int Tex6Index : 6;
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int Tex7Index : 6;
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};
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uint32_t bits;
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};
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union VCD_Lo
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{
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struct
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{
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bool PosNrmMatIdx : 1;
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bool Tex0MatIdx : 1;
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bool Tex1MatIdx : 1;
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bool Tex2MatIdx : 1;
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bool Tex3MatIdx : 1;
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bool Tex4MatIdx : 1;
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bool Tex5MatIdx : 1;
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bool Tex6MatIdx : 1;
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bool Tex7MatIdx : 1;
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AttrType Position : 2;
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AttrType Normal : 2;
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AttrType Color0 : 2;
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AttrType Color1 : 2;
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};
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uint32_t bits;
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};
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union VCD_Hi
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{
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struct
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{
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AttrType Tex0Coord : 2;
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AttrType Tex1Coord : 2;
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AttrType Tex2Coord : 2;
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AttrType Tex3Coord : 2;
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AttrType Tex4Coord : 2;
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AttrType Tex5Coord : 2;
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AttrType Tex6Coord : 2;
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AttrType Tex7Coord : 2;
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};
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uint32_t bits;
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};
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union VAT_group0
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{
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struct
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{
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VatCount poscnt : 1;
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VatFormat posfmt : 3;
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size_t posshft : 5; // Location of decimal point from LSB. This shift applies to all u/short components and to u/byte components where ByteDequant is asserted
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VatCount nrmcnt : 1;
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VatFormat nrmfmt : 3; // Normal location of decimal point predefined as follow: Byte: 6, Short: 14
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VatCount col0cnt : 1;
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VatFormat col0fmt : 3;
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VatCount col1cnt : 1;
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VatFormat col1fmt : 3;
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VatCount tex0cnt : 1;
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VatFormat tex0fmt : 3;
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size_t tex0shft : 5;
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bool bytedeq : 1; // Shift applies for u/byte and u/short components of position and texture attributes.
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bool nrmidx3 : 1; // When nine normals selected in indirect mode, input will be treated as three staggered indices (one per triple biased by component size), into normal table.
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};
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uint32_t bits;
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};
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union VAT_group1
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{
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struct
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{
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VatCount tex1cnt : 1;
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VatFormat tex1fmt : 3;
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size_t tex1shft : 5;
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VatCount tex2cnt : 1;
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VatFormat tex2fmt : 3;
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size_t tex2shft : 5;
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VatCount tex3cnt : 1;
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VatFormat tex3fmt : 3;
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size_t tex3shft : 5;
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VatCount tex4cnt : 1;
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VatFormat tex4fmt : 3;
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bool vcache : 1;
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};
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uint32_t bits;
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};
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union VAT_group2
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{
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struct
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{
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size_t tex4shft : 5;
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VatCount tex5cnt : 1;
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VatFormat tex5fmt : 3;
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size_t tex5shft : 5;
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VatCount tex6cnt : 1;
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VatFormat tex6fmt : 3;
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size_t tex6shft : 5;
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VatCount tex7cnt : 1;
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VatFormat tex7fmt : 3;
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size_t tex7shft : 5;
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};
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uint32_t bits;
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};
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union ArrayBase
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{
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struct
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{
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uint32_t Base : 26;
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};
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uint32_t bits;
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};
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union ArrayStride
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{
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struct
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{
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int Stride : 8;
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};
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uint32_t bits;
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};
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// Array name for ArrayBase and ArrayStride
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enum class ArrayId
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{
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Pos = 0,
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Nrm,
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Color0,
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Color1,
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Tex0Coord,
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Tex1Coord,
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Tex2Coord,
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Tex3Coord,
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Tex4Coord,
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Tex5Coord,
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Tex6Coord,
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Tex7Coord,
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// Used by XF_IndexLoadRegA/B/C/D commands
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IndexRegA,
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IndexRegB,
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IndexRegC,
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IndexRegD,
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Max,
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};
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struct CPState
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{
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MatrixIndexA matIndexA; // 0011xxxx
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MatrixIndexB matIndexB; // 0100xxxx
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VCD_Lo vcdLo; // 0101xxxx
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VCD_Hi vcdHi; // 0110xxxx
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VAT_group0 vatA[8]; // 0111x,vat[2:0]
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VAT_group1 vatB[8]; // 1000x,vat[2:0]
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VAT_group2 vatC[8]; // 1001x,vat[2:0]
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ArrayBase arrayBase[(size_t)ArrayId::Max]; // 1010,array[3:0]
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ArrayStride arrayStride[(size_t)ArrayId::Max]; // 1011,array[3:0]
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};
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#pragma pack(pop)
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}
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