mirror of
https://github.com/emu-russia/pureikyubu.git
synced 2025-04-02 10:42:15 -04:00
90 lines
3.3 KiB
C
90 lines
3.3 KiB
C
// Flipper memory controller
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// GC physical memory map.
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/*/
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00000000 24MB Main Memory (RAM)
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08000000 2MB Embedded Framebuffer (EFB)
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0C000000 Command Processor (CP)
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0C001000 Pixel Engine (PE)
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0C002000 Video Interface (VI)
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0C003000 Processor Interface (PI)
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0C004000 Memory Interface (MI)
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0C005000 DSP and DMA Audio Interface (AID)
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0C006000 DVD Interface (DI)
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0C006400 Serial Interface (SI)
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0C006800 External Interface (EXI)
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0C006C00 Audio Streaming Interface (AIS)
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0C008000 GX FIFO
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FFF00000 2MB Boot ROM
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EFB - this is not straight "direct" access. reads and writes
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are passing through some Flipper logic, so its just simulation of
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direct access.
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Hardware Registers (HW) are located above 0x0C000000. Dolwin
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memory engine is using hardware traps, which are handling all
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registers operations. traps are abstracting HW from Emulator,
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so basically any Hardware will work with Dolwin, with minimal
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modifications of Emulator core.
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Boot ROM is available only during CPU reset. after reset,
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execution will begin from 0xFFF00100 reset vector, with
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enabled bootrom EXI reading logic. small program, called
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"BS" (Bootstrap?) will run and load IPL menu up to
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0x81300000 address (already effective!). then IPL menu (or "BS2")
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will run, with disabled EXI scrambler.
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/*/
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#pragma once
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// amount of main memory (in bytes)
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#define RAMSIZE 0x01800000 // 24 mb
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// Bootrom size (in bytes)
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#define BOOTROM_SIZE (2*1024*1024)
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// Bootrom start address
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#define BOOTROM_START_ADDRESS 0xfff00000
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// physical memory mask (for simple translation mode).
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// 0x0fffffff, because GC architecture is limited by 256 mb of RAM
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#define RAMMASK 0x0fffffff
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// max known GC HW address is 0x0C008004 (fifo), so 0x8010 will be enough.
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// note : it must not be greater 0xffff, unless you need to change code.
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#define HW_MAX_KNOWN 0x8010
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void MIReadByte(uint32_t phys_addr, uint32_t* reg);
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void MIWriteByte(uint32_t phys_addr, uint32_t data);
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void MIReadHalf(uint32_t phys_addr, uint32_t* reg);
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void MIWriteHalf(uint32_t phys_addr, uint32_t data);
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void MIReadWord(uint32_t phys_addr, uint32_t* reg);
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void MIWriteWord(uint32_t phys_addr, uint32_t data);
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void MIReadDouble(uint32_t phys_addr, uint64_t* reg);
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void MIWriteDouble(uint32_t phys_addr, uint64_t* data);
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void MIReadBurst(uint32_t phys_addr, uint8_t burstData[32]);
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void MIWriteBurst(uint32_t phys_addr, uint8_t burstData[32]);
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struct MIControl
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{
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uint8_t* ram;
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size_t ramSize;
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uint8_t* bootrom; ///< Descrambled (Thank you segher, you already have a place in heaven)
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size_t bootromSize;
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bool BootromPresent; ///< loaded and descrambled valid bootrom
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};
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extern MIControl mi;
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void MISetTrap(
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uint32_t type, // 8, 16 or 32
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uint32_t addr, // physical address of trap
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void (*rdTrap)(uint32_t, uint32_t*) = NULL, // register read trap
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void (*wrTrap)(uint32_t, uint32_t) = NULL); // register write trap
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void MIOpen(HWConfig * config);
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void MIClose();
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uint8_t* MITranslatePhysicalAddress(uint32_t physAddr, size_t bytes);
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