mirror of
https://github.com/emu-russia/pureikyubu.git
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140 lines
3.4 KiB
C++
140 lines
3.4 KiB
C++
// DSP ARAM Accelerator
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// Accelerator addresses work in accordance with the selected mode (4-bit, 8-bit, 16-bit).
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// That is, for example, in 4-bit mode - the start, current and end addresses point to nibble in ARAM.
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// On a real system, the next piece of data is cached in 3 16-bit registers ("output ports").
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// Here we do not repeat this mechanism, but refer directly to ARAM.
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// The accelerator can work both independently, simply driving data between ARAM and DSP, and in conjunction with an ADPCM decoder.
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// In the first case, one register is used (ACDAT, read-write), in the second case, another (ACDAT2, read-only).
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#include "pch.h"
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using namespace Debug;
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namespace DSP
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{
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uint16_t DspCore::AccelFetch()
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{
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uint16_t val = 0;
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uint8_t tempByte = 0;
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switch (Accel.Fmt & 3)
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{
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case 0:
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// Refresh pred/scale
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if ((Accel.CurrAddress.addr & 0xF) == 0 && ((Accel.Fmt >> 2) & 3) == 0)
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{
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Accel.AdpcmPds = *(uint8_t*)(aram.mem + (Accel.CurrAddress.addr & 0x07ff'ffff) / 2);
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Accel.CurrAddress.addr += 2;
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}
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// TODO: Check currAddr == endAddr after Pred/Scale update.
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tempByte = *(uint8_t*)(aram.mem + (Accel.CurrAddress.addr & 0x07ff'ffff) / 2);
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if ((Accel.CurrAddress.addr & 1) == 0)
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{
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val = tempByte >> 4; // High nibble
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}
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else
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{
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val = tempByte & 0xf; // Low nibble
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}
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break;
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case 1:
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val = *(uint8_t*)(aram.mem + (Accel.CurrAddress.addr & 0x07ff'ffff));
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break;
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case 2:
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val = _byteswap_ushort(*(uint16_t*)(aram.mem + 2 * (uint64_t)(Accel.CurrAddress.addr & 0x07ff'ffff)));
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break;
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default:
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Halt("DSP: Invalid accelerator mode: 0x%04X\n", Accel.Fmt);
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break;
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}
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Accel.CurrAddress.addr++;
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if ((Accel.CurrAddress.addr & 0x07ff'ffff) >= (Accel.EndAddress.addr & 0x07FF'FFFF))
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{
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Accel.CurrAddress.addr = Accel.StartAddress.addr;
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if (logAccel)
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{
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Report(Channel::DSP, "Accelerator Overflow while read\n");
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}
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if (regs.sr.ge && regs.sr.acie)
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{
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Accel.pendingOverflow = true;
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Accel.overflowVector = ((Accel.Fmt >> 3) & 3) == 0 ? DspException::ADP_OVF : DspException::ACR_OVF;
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}
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}
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return val;
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}
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// Read data by accelerator and optionally decode (raw=false)
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uint16_t DspCore::AccelReadData(bool raw)
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{
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uint16_t val = 0;
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// Check bit15 of ACCAH
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if ((Accel.CurrAddress.h & 0x8000) != 0)
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{
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// This is #UB
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Halt("DSP: Accelerator is not configured to read\n");
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}
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val = AccelFetch();
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// Issue ADPCM Decoder
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if (!raw)
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{
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val = DecodeAdpcm(val);
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}
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return val;
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}
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// Write RAW data to ARAM
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void DspCore::AccelWriteData(uint16_t data)
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{
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// Check bit15 of ACCAH
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if ((Accel.CurrAddress.h & 0x8000) == 0)
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{
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// This is #UB
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Halt("DSP: Accelerator is not configured to write\n");
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}
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// Write mode is always 16-bit
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*(uint16_t*)(aram.mem + 2 * (uint64_t)(Accel.CurrAddress.addr & 0x07ff'ffff)) = _byteswap_ushort(data);
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Accel.CurrAddress.addr++;
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if ((Accel.CurrAddress.addr & 0x07ff'ffff) >= (Accel.EndAddress.addr & 0x07FF'FFFF))
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{
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Accel.CurrAddress.addr = Accel.StartAddress.addr;
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Accel.CurrAddress.h |= 0x8000;
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if (logAccel)
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{
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Report(Channel::DSP, "Accelerator Overflow while write\n");
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}
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if (regs.sr.ge && regs.sr.acie)
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{
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Accel.pendingOverflow = true;
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Accel.overflowVector = DspException::ACW_OVF;
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}
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}
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}
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void DspCore::ResetAccel()
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{
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Accel.pendingOverflow = false;
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}
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}
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