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https://github.com/emu-russia/pureikyubu.git
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95 lines
4.5 KiB
C++
95 lines
4.5 KiB
C++
#pragma once
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// AI registers (AID regs are 16-bit, AIS regs are 32-bit)
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#define DSP_OUTMBOXH 0x0C005000 // CPU->DSP mailbox
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#define DSP_OUTMBOXL 0x0C005002
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#define DSP_INMBOXH 0x0C005004 // DSP->CPU mailbox
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#define DSP_INMBOXL 0x0C005006
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#define AI_DCR 0x0C00500A // AI/DSP control register
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#define AID_MADRH 0x0C005030 // DMA start address (High)
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#define AID_MADRL 0x0C005032 // DMA start address (Low)
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#define AID_LEN 0x0C005036 // DMA control/DMA length (length of audio data in 32 Byte blocks)
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#define AID_CNT 0x0C00503A // counts down to zero showing how many 32 Byte blocks are left
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#define AIS_CR 0x0C006C00 // AIS control register
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#define AIS_VR 0x0C006C04 // AIS volume register
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#define AIS_SCNT 0x0C006C08 // AIS sample counter
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#define AIS_IT 0x0C006C0C // AIS interrupt timing
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// AI/DSP Control Register mask (bits 10 and 11 are unknown)
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#define AIDCR_UNKNOWN_11 (1 << 11) // Clear bit11 ---\ Used in OSInitAudioSystem
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#define AIDCR_UNKNOWN_10 (1 << 10) // Wait until bit10 not clear <--/
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#define AIDCR_DSPDMA (1 << 9) // DSP dma in progress
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#define AIDCR_DSPINTMSK (1 << 8) // DSP->CPU interrupt mask (ReadWrite)
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#define AIDCR_DSPINT (1 << 7) // DSP->CPU interrupt status (ReadWrite-Clear)
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#define AIDCR_ARINTMSK (1 << 6) // ARAM DMA interrupt mask (RW)
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#define AIDCR_ARINT (1 << 5) // ARAM DMA interrupt status (RWC)
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#define AIDCR_AIINTMSK (1 << 4) // AI DMA interrupt mask (RW)
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#define AIDCR_AIINT (1 << 3) // AI DMA interrupt status (RWC)
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#define AIDCR_HALT (1 << 2) // halt DSP (stop ucoding)
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#define AIDCR_DINT (1 << 1) // CPU->DSP interrupt
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#define AIDCR_RES (1 << 0) // reset DSP (waits for 0)
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// enable bit in AIDLEN register
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#define AID_EN (1 << 15)
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// Audio Interface Control Register mask
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#define AICR_DFR (1 << 6) // AID sample rate (HW2 only). 0 - 48000, 1 - 32000
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#define AICR_SCRESET (1 << 5) // reset sample counter
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#define AICR_AIINTVLD (1 << 4) // This bit controls whether AIINT is affected by the AIIT register matching (0 - match affects, 1 - not)
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#define AICR_AIINT (1 << 3) // AIS interrupt status
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#define AICR_AIINTMSK (1 << 2) // AIS interrupt mask
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#define AICR_AFR (1 << 1) // AIS sample rate. 0 - 32000, 1 - 48000
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#define AICR_PSTAT (1 << 0) // This bit enables the DDU AISLR clock
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#define AIDCR ai.dcr
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// double-buffered register, to make safe 16-bit regs access
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// register assumed to be correct, only when both shadows are valid
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typedef struct AIREG
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{
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bool valid[2]; // shadow valid state
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struct { uint16_t hi, lo; } shadow; // register data
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} AIREG;
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// ---------------------------------------------------------------------------
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// hardware API
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// AI state (registers and other data)
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typedef struct AIControl
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{
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// AID
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std::atomic<uint16_t> dcr; // AI/DSP control register
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volatile AIREG madr; // DMA address
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volatile uint16_t len; // DMA control/DMA length (length of audio data)
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volatile uint16_t dcnt; // DMA count-down
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// AIS
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volatile uint32_t cr; // AIS control reg
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volatile uint32_t vr; // AIS volume
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volatile uint32_t scnt; // sample counter
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volatile uint32_t it; // sample counter trigger
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// helpers
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uint32_t currentDmaAddr; // current DMA address
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int32_t dmaRate; // copy of DFR value (32000/48000)
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uint64_t dmaTime; // audio DMA update time
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Thread* audioThread; // The main AI thread that receives samples from AI DMA FIFO and DVD Audio (which accumulate in AIS FIFO).
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// When FIFOs overflow - AudioThread Feed Mixer.
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uint8_t streamFifo[32];
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size_t streamFifoPtr;
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int64_t one_second; // one CPU second in timer ticks
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bool log; // Enable AI log
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} AIControl;
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extern AIControl ai;
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void AIOpen(HWConfig * config);
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void AIClose();
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// Used by DspCore
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void DSPAssertInt();
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bool DSPGetInterruptStatus();
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