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Docs: New TODO moved to EMU, old renamed to old_todo Docs: Old coding style is deprecated (old_style.txt) Docs: Removed mention about CubeDocumented and fixed old emails RE: boot.s, proved first asm line (lis instruction parameter) RE: Added PAL and NTSC Boot and IPL IDA files RE: Some work on NTSC IPL (identified many lib calls, including OS, GX) RE: Added EXI Bootrom descrambler by segher RE: GXInit RE: Internal GX lib structures (GXPrivate.h) RE: More details on lomem (OS versions) RE: OSInit and OS.c RE: OSAlloc (heap allocator) RE: Very first code of Metrowerk runtime (__start.c) Docs: Added copy of http://gcdev.narod.ru Source\Utils: Command processor (Cmd.c) Source\Utils: File wrapper Source\Utils: Gekko disasm cleaned up and ported to plain C Source\Utils: Double-linked lists Source\Utils: Ported old Profiler code Source\Utils: String utils
501 lines
19 KiB
Text
501 lines
19 KiB
Text
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= Dolphin OS interrupt handling reversing by org. =
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This document can help you to create your own GAMECUBE interrupt handling
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code (even in your own OS?). I hope it will be also useful for authors of
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GC emulators. Send your comments or questions to ogamespec@gmail.com
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1. Overview.
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PPC has so called, "external interrupt enable" bit, in MSR register
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(MSR[EE] later). External interrupt is generated only when this bit is set.
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(Actually, this bit is not allowing to raise interrupt signal in CPU).
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Here is some pseudo-code for interrupt control :
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---------------------------------------------------------------------------
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BOOL OSEnableInterrupts(void)
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{
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u32 prev = MSR;
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MSR |= MSR_EE;
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return (prev >> 15) & 1;
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}
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BOOL OSDisableInterrupts(void)
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{
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u32 prev = MSR;
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MSR &= ~MSR_EE;
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return (prev >> 15) & 1;
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}
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---------------------------------------------------------------------------
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External interrupt exception handler is placed at 0x500 memory location
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in OS "lomem" area. Initialization and OS interrupt handling will be
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described later.
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CPU also have access to hardware interrupt mask and cause registers,
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placed in PI (Processor Interface) :
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0C003000 - Interrupt cause (32-bit, R)
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0C003004 - Interrupt mask (32-bit, R/W)
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Referred also as INTSR and INTMR respectively.
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Note, that given registers location is in physical memory (means raw
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address for CPU bus transfers). Dolphin OS default memory configuration
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will map all registers to CC000000 and above, so as example, INTSR will be
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CC003000.
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INTSR and INTMR mask bit layout (big-endian) :
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-----------------------------------------------------------
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| bit | name | mask | short description | total |
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|=====|===========|============|============================|
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| 15 | RSWST | 0x00010000 | Reset switch state | * |
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| 18 | HSP | 0x00002000 | High-speed port | 1? |
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| 19 | DEBUG | 0x00001000 | External debugger | 1? |
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| 20 | CP | 0x00000800 | Command FIFO | 3 |
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| 21 | PE FINISH | 0x00000400 | Frame is ready | 1 |
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| 22 | PE TOKEN | 0x00000200 | Token assertion | 1 |
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| 23 | VI | 0x00000100 | VI line | 4 |
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| 24 | MEM | 0x00000080 | Memory protection | 5 |
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| 25 | DSP | 0x00000040 | DSP | 3 |
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| 26 | AI | 0x00000020 | Streaming | 1 |
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| 27 | EXI | 0x00000010 | EXI interrupts | 8 |
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| 28 | SI | 0x00000008 | Serial transfer | 2 |
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| 29 | DI | 0x00000004 | Disk | 3 |
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| 30 | RSW | 0x00000002 | Reset switch | 1 |
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| 31 | ERROR | 0x00000001 | GP verify error | 1? |
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-----------------------------------------------------------
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* Only for INTSR. This bit is not used in interrupt handling.
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Actually, each hardware interrupt have several of different interrupts,
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with one common enable/disable flag. Some documents are referring them
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as "sources". As example VI have 4 line interrupts (thus 4 sources),
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you can disable any of them, using VI registers, but PI mask disables them
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all at once.
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More to say, that interrupt controlling bits in source device registers
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are "linked" in some way with INTSR. Im not sure about all details, but it
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seems that INTSR is working in tricky way. When "interrupt set" bits are
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cleared in source device, corresponding device bit is also cleared in INTSR.
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As example :
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AIDCR has ARINT bit. when ARAM transfer complete interrupt will
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generate, this bit will set. At same time, INTSR DSP bit will set.
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Then external interrupt signal will be generated to CPU, and it
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jumps to interrupt handler (if MSR[EE] allowing it). OS interrupt
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dispatch handler transfer control to ARAM handler in ARAM library.
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And finally ARAM handler will clear ARINT bit in AIDCR. At same
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time (when AIDCR cleared) hardware will clear DSP bit in INTSR.
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Important note : interrupt mask register also used by hardware. It is not
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allowing to raise interrupt signal to CPU, but it doesnt affect setting
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of INTSR bit :
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INTSR |= interrupt;
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if(interrupt & INTMR)
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{
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Exception(EXTERNAL_INTERRUPT)
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}
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So OS interrupt handler can take care about delayed interrupts in future.
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OS has handy API, to enable specified interrupt and install interrupt
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handlers. This API is using its own interrupt mask, just for convenience :
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-------------------------------------------------------------------------
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| bit | name | mask | short description |
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|=====|=============|============|========================================|
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| 0 | MEM 0 | 0x80000000 | Memory page protection interrupts |
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| 1 | MEM 1 | 0x40000000 | |
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| 2 | MEM 2 | 0x20000000 | |
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| 3 | MEM 3 | 0x10000000 | |
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| 4 | MEM ADDRESS | 0x08000000 | General memory protection |
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| 5 | DSP AI | 0x04000000 | AI DMA interrupt |
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| 6 | DSP ARAM | 0x02000000 | ARAM transfer completed |
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| 7 | DSP DSP | 0x01000000 | DSP interrupt (reset, halt, mailbox) |
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| 8 | AI AI | 0x00800000 | Streamed sample counter interrupt |
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| 9 | EXI 0 EXI | 0x00400000 | EXI hardware interrupts : |
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| 10 | EXI 0 TC | 0x00200000 | |
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| 11 | EXI 0 EXT | 0x00100000 | EXI - external device attached |
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| 12 | EXI 1 EXI | 0x00080000 | EXT - external device detached |
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| 13 | EXI 1 TC | 0x00040000 | TC - EXI bus transfer completed |
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| 14 | EXI 1 EXT | 0x00020000 | |
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| 15 | EXI 2 EXI | 0x00010000 | |
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| 16 | EXI 2 TC | 0x00008000 | |
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| 17 | CP | 0x00004000 | See above |
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| 18 | PE TOKEN | 0x00002000 | |
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| 19 | PE FINISH | 0x00001000 | |
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| 20 | SI | 0x00000800 | Serial interrupts |
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| 21 | DI | 0x00000400 | Disk interrupt |
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| 22 | RSW | 0x00000200 | Reset switch pressed / released |
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| 23 | ERROR | 0x00000100 | Various GX hardware errors |
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| 24 | VI | 0x00000080 | VI retrace (assumed as line 0) |
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| 25 | DEBUG | 0x00000040 | Debug hardware (GDEV, DDH) |
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| 26 | HSP | 0x00000020 | High-speed port |
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-------------------------------------------------------------------------
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2. Interrupt OS initialization.
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Initialization of exceptions and interrupts is located in OSInit() :
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---------------------------------------------------------------------------
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void OSInit(void)
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{
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...
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// install default exception handlers
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OSExceptionInit();
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.
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.
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.
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// install default interrupt handler
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__OSInterruptInit();
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...
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}
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---------------------------------------------------------------------------
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First we must install default exception "stubs" to prevent crashes from
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unhandled exception. Here is default exception handler :
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---------------------------------------------------------------------------
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void OSDefaultExceptionHandler(__OSException exception, OSContext *context, u32 dsisr, u32 dar)
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{
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// Save context (see OSException.h)
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OS_EXCEPTION_SAVE_GPRS(context);
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// Take control to unhandled exception handler (halt the system)
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__OSUnhandledException(exception, context, dsisr, dar);
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}
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(Exception initialization code is not shown here)
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---------------------------------------------------------------------------
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After that, __OSInterruptInit() installs interrupt exception handler :
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---------------------------------------------------------------------------
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u32 __OSPrevInterruptMask AT_ADDRESS(OS_BASE_CACHED | 0x00C4);
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u32 __OSInterruptMask AT_ADDRESS(OS_BASE_CACHED | 0x00C8);
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void (*InterruptHandlerTable[32])( // installed handlers
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__OSInterrupt interrupt,
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OSContext* context
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);
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void *(*__OSInterruptHandlerTable[32])( // duplicate pointer for debug
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__OSInterrupt interrupt,
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OSContext* context
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) AT_ADDRESS(OS_BASE_CACHED | 0x3040);
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void __OSInterruptInit()
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{
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// Save interrupt table pointer in lomem (for debugger)
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*__OSInterruptHandlerTable = InterruptHandlerTable;
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// Clear interrupt table
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memset(InterruptHandlerTable, 0, sizeof(InterruptHandlerTable));
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// Masks
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__OSPrevInterruptMask = 0; // clear prev OS interrupt mask
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*(u32 *)0xCC003004 = 0x000000F0; // set PI interrupt mask
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__OSMaskInterrupts(0xFFFFFFE0); // mask all interrupts
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// Set interrupt exception handler at 0x500
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__OSSetExceptionHandler(__OS_EXCEPTION_EXTERNAL_INTERRUPT, ExternalInterruptHandler);
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}
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void ExternalInterruptHandler(__OSException exception, OSContext *context, u32 dsisr, u32 dar)
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{
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#pragma unused (dsisr)
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#pragma unused (dar)
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// Save context (see OSException.h)
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OS_EXCEPTION_SAVE_GPRS(context);
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// Transfer control to interrupt dispatch handler
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__OSDispatchInterrupt(exception, context);
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}
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---------------------------------------------------------------------------
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Interrupt dispatch handler is major driving force in thread switching.
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Dolphin OS is rescheduling active threads after every interrupt, so it
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doesnt have fixed "time slice" interval. But it guarantees, that threads
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are rescheduling at least every 1/50 seconds (1/60, 1/25, 1/30 - depending
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on video mode and interlace). It is very important detail for high level
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GC emulators.
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BTW, such thread switching behaviour is bringing unstability in Dolphin OS.
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Thats why some games are showing "Green Screen of Death" sometimes.
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Nintendo probably should add following patch in __OSReschedule routine :
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static OSTime TimeSlice;
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void __OSReschedule(void)
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{
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OSTime now = OSGetTime();
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if((now - TimeSlice) >= OSMillisecondsToTicks(20))
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{
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TimeSlice = now;
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}
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else return; // not yet..
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// reschedule
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..
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..
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}
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---------------------------------------------------------------------------
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// hardware interrupt mask
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#define PI_INTERRUPT_HSP 0x2000
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#define PI_INTERRUPT_DEBUG 0x1000
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#define PI_INTERRUPT_CP 0x0800
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#define PI_INTERRUPT_PE_FINISH 0x0400
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#define PI_INTERRUPT_PE_TOKEN 0x0200
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#define PI_INTERRUPT_VI 0x0100
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#define PI_INTERRUPT_MEM 0x0080
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#define PI_INTERRUPT_DSP 0x0040
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#define PI_INTERRUPT_AI 0x0020
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#define PI_INTERRUPT_EXI 0x0010
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#define PI_INTERRUPT_SI 0x0008
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#define PI_INTERRUPT_DI 0x0004
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#define PI_INTERRUPT_RSW 0x0002
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#define PI_INTERRUPT_ERROR 0x0001
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// Handle incoming interrupts and reschedule threads
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void __OSDispatchInterrupt(OSContext *context)
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{
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u32 intsr, cause;
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u32 unmasked, *prio;
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__OSInterrupt interrupt;
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__OSInterruptHandler handler;
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intsr = *(u32 *)0xCC003000 & ~0x10000; // we no need RSW state
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// return, if no interrupts pending, or interrupts are masked
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if( (intsr == 0) || ((intsr & *(u32 *)0xCC003004) == 0) )
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{
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OSLoadContext(context);
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}
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// its time to collect interrupts
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cause = 0;
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if(intsr & PI_INTERRUPT_MEM)
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{
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u16 reg = *(u16 *)0xCC00401E; // MI interrupt cause
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if(reg & 0x0001) cause |= OS_INTERRUPTMASK_MEM_0;
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if(reg & 0x0002) cause |= OS_INTERRUPTMASK_MEM_1;
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if(reg & 0x0004) cause |= OS_INTERRUPTMASK_MEM_2;
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if(reg & 0x0008) cause |= OS_INTERRUPTMASK_MEM_3;
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if(reg & 0x0010) cause |= OS_INTERRUPTMASK_MEM_ADDRESS;
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}
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// Audio DMA counter=0, ARAM transfer complete or DSP interrupt
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if(intsr & PI_INTERRUPT_DSP)
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{
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u16 reg = *(u16 *)0xCC00500A; // AIDCR
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if(reg & 0x0008) cause |= OS_INTERRUPTMASK_DSP_AI;
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if(reg & 0x0020) cause |= OS_INTERRUPTMASK_DSP_ARAM;
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if(reg & 0x0080) cause |= OS_INTERRUPTMASK_DSP_DSP;
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}
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// Disk streaming sample counter=trigger
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if(intsr & PI_INTERRUPT_AI)
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{
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u32 reg = *(u32 *)0xCC006C00; // AICR
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if(reg & 0x0008) cause |= OS_INTERRUPTMASK_AI;
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}
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// EXI bus interrupts
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if(intsr & PI_INTERRUPT_EXI)
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{
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u32 reg = *(u32 *)0xCC006800; // EXI0 CSR
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if(reg & 0x0002) cause |= OS_INTERRUPTMASK_EXI_0_EXI;
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if(reg & 0x0008) cause |= OS_INTERRUPTMASK_EXI_0_TC;
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if(reg & 0x0800) cause |= OS_INTERRUPTMASK_EXI_0_EXT;
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u32 reg = *(u32 *)0xCC006814; // EXI1 CSR
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if(reg & 0x0002) cause |= OS_INTERRUPTMASK_EXI_1_EXI;
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if(reg & 0x0008) cause |= OS_INTERRUPTMASK_EXI_1_TC;
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if(reg & 0x0800) cause |= OS_INTERRUPTMASK_EXI_1_EXT;
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u32 reg = *(u32 *)0xCC006828; // EXI2 CSR
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if(reg & 0x0002) cause |= OS_INTERRUPTMASK_EXI_2_EXI;
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if(reg & 0x0008) cause |= OS_INTERRUPTMASK_EXI_2_TC;
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}
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// No information
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if(intsr & PI_INTERRUPT_HSP)
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{
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cause |= OS_INTERRUPTMASK_PI_HSP;
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}
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// No information
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if(intsr & PI_INTERRUPT_DEBUG)
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{
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cause |= OS_INTERRUPTMASK_PI_DEBUG;
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}
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// Frame is ready ("draw done")
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if(intsr & PI_INTERRUPT_PE_FINISH)
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{
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cause |= OS_INTERRUPTMASK_PI_PE_FINISH;
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}
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// Token marker ("draw sync")
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if(intsr & PI_INTERRUPT_PE_TOKEN)
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{
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cause |= OS_INTERRUPTMASK_PI_PE_TOKEN;
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}
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// VI specially configured to generate only one interrupt.
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// It is assigned at line 0 (or at last line, not sure),
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// and thus its called vertical retrace interrupt.
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// Nintendo also planning to add horizontal retrace interrupt in future.
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// (I dont see any advantages of it, though).
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if(intsr & PI_INTERRUPT_VI)
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{
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cause |= OS_INTERRUPTMASK_PI_VI;
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}
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// Serial transfer complete or "RDST" interrupt
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if(intsr & PI_INTERRUPT_SI)
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{
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cause |= OS_INTERRUPTMASK_PI_SI;
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}
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// Disk transfer complete, cover opened/closed or DVD break operation
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if(intsr & PI_INTERRUPT_DI)
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{
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cause |= OS_INTERRUPTMASK_PI_DI;
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}
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// Reset button pressed/released
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if(intsr & PI_INTERRUPT_RSW)
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{
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cause |= OS_INTERRUPTMASK_PI_RSW;
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}
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// Command processor fifo underflow, overflow or breakpoint
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if(intsr & PI_INTERRUPT_CP)
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{
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cause |= OS_INTERRUPTMASK_PI_CP;
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}
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// No information
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if(intsr & PI_INTERRUPT_ERROR)
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{
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cause |= OS_INTERRUPTMASK_PI_ERROR;
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}
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if(cause &= ~(__OSPrevInterruptMask | __OSInterruptMask))
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{
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prio = InterruptPrioTable;
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for(;;)
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{
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if(unmasked = *prio & cause)
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{
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interrupt = cntlzw(unmasked);
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break;
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} else prio++;
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}
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if(handler = InterruptHandlerTable[interrupt])
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{
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if(interrupt >= __OS_INTERRUPT_DSP_AI)
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{
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__OSLastInterrupt = interrupt;
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__OSLastInterruptTime = OSGetTime();
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__OSLastInterruptSrr0 = context->srr0;
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}
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OSDisableScheduler();
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handler(interrupt, context);
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OSEnableScheduler();
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__OSReschedule();
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OSLoadContext(context);
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}
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}
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OSLoadContext(context);
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}
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// priority table (high->low)
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u32 InterruptPrioTable[] = {
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OS_INTERRUPTMASK_PI_ERROR,
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OS_INTERRUPTMASK_PI_DEBUG,
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OS_INTERRUPTMASK_MEM,
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OS_INTERRUPTMASK_PI_RSW,
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OS_INTERRUPTMASK_PI_VI,
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OS_INTERRUPTMASK_PI_PE,
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OS_INTERRUPTMASK_PI_HSP,
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OS_INTERRUPTMASK_DSP_ARAM |
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OS_INTERRUPTMASK_DSP_DSP |
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OS_INTERRUPTMASK_AI |
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OS_INTERRUPTMASK_EXI |
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OS_INTERRUPTMASK_PI_SI |
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OS_INTERRUPTMASK_PI_DI,
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OS_INTERRUPTMASK_DSP_AI,
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OS_INTERRUPTMASK_PI_CP,
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0xffffffff
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};
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3. Interrupt masking (to be added).
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OSInterruptMask OSGetInterruptMask(void)
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{
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return __OSInterruptMask;
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}
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OSInterruptMask OSSetInterruptMask(OSInterruptMask mask)
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{
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}
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OSInterruptMask __OSMaskInterrupts(OSInterruptMask mask)
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{
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}
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OSInterruptMask __OSUnmaskInterrupts(OSInterruptMask mask)
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{
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}
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4. Setting interrupt handlers.
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__OSInterruptHandler __OSSetInterruptHandler(__OSInterrupt interrupt, __OSInterruptHandler handler)
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{
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InterruptHandlerTable[interrupt] = handler;
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}
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__OSInterruptHandler __OSGetInterruptHandler(__OSInterrupt interrupt)
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{
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return InterruptHandlerTable[interrupt];
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}
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---------------------------------------------------------------------------
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Referencies :
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except.txt - For exceptions info
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context.txt - See for details of OS context switching
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thread.txt - Reversing of OS thread management
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This document is maintaining by Dolwin team.
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Last edited by org, 15 Aug 2004
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