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https://github.com/emu-russia/pureikyubu.git
synced 2025-04-02 10:42:15 -04:00
c91662b127
- RTI in analyzer - IROM mapped in DMEM - ARAM -> IRAM DMA size multiplied by 4 - OSInitAudioSystem stub reversing
108 lines
4.3 KiB
Text
108 lines
4.3 KiB
Text
// DSP mailbox registers
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#define DSP_OUTMBOXH *(volatile u16 *)(0xCC005000)
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#define DSP_OUTMBOXL *(volatile u16 *)(0xCC005002)
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#define DSP_INMBOXH *(volatile u16 *)(0xCC005004)
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#define DSP_INMBOXL *(volatile u16 *)(0xCC005006)
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// known ARAM controller registers
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#define AR_SIZE (*(volatile u16 *)(0xCC005012)) // 16 bit regs
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#define AR_MODE (*(volatile u16 *)(0xCC005016))
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#define AR_REFRESH (*(volatile u16 *)(0xCC00501A))
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#define AR_DMA_MMADDR_H (*(volatile u16 *)(0xCC005020))
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#define AR_DMA_MMADDR_L (*(volatile u16 *)(0xCC005022))
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#define AR_DMA_ARADDR_H (*(volatile u16 *)(0xCC005024))
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#define AR_DMA_ARADDR_L (*(volatile u16 *)(0xCC005026))
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#define AR_DMA_CNT_H (*(volatile u16 *)(0xCC005028))
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#define AR_DMA_CNT_L (*(volatile u16 *)(0xCC00502A))
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#define AR_DMA_MMADDR (*(volatile u16 *)(0xCC005020)) // 32 bit regs
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#define AR_DMA_ARADDR (*(volatile u16 *)(0xCC005024))
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#define AR_DMA_CNT (*(volatile u16 *)(0xCC005028))
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// DSP interface main control register
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#define AIDCR (*(volatile u16 *)(0xCC00500A))
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// AIDCR bits (bits 10 and 11 are unknown)
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#define AIDCR_DSPDMA (1 << 9) // dsp task dma in progress, if set
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#define AIDCR_DSPINTMSK (1 << 8) // dsp interrupt mask (RW)
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#define AIDCR_DSPINT (1 << 7) // dsp interrupt active (RWC)
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#define AIDCR_ARINTMSK (1 << 6)
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#define AIDCR_ARINT (1 << 5)
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#define AIDCR_AIINTMSK (1 << 4)
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#define AIDCR_AIINT (1 << 3)
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#define AIDCR_HALT (1 << 2) // halt DSP
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#define AIDCR_PIINT (1 << 1) // assert DSP PI interrupt
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#define AIDCR_RES (1 << 0) // reset DSP
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static u16 DSPInitCode[0x40] = { // 128 bytes
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0x029F, 0x0010, 0x029F, 0x0033, 0x029F, 0x0034, 0x029F, 0x0035,
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0x029F, 0x0036, 0x029F, 0x0037, 0x029F, 0x0038, 0x029F, 0x0039,
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0x1206, 0x1203, 0x1204, 0x1205, 0x0080, 0x8000, 0x0088, 0xFFFF,
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0x0084, 0x1000, 0x0064, 0x001D, 0x0218, 0x0000, 0x8100, 0x1C1E,
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0x0044, 0x1B1E, 0x0084, 0x0800, 0x0064, 0x0027, 0x191E, 0x0000,
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0x00DE, 0xFFFC, 0x02A0, 0x8000, 0x029C, 0x0028, 0x16FC, 0x0054,
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0x16FD, 0x4348, 0x0021, 0x02FF, 0x02FF, 0x02FF, 0x02FF, 0x02FF,
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0x02FF, 0x02FF, 0x02FF, 0x02FF, 0x0000, 0x0000, 0x0000, 0x0000,
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};
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// ---------------------------------------------------------------------------
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void __OSInitAudioSystem()
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{
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// copy DSP init ucode to 32B aligned memory area
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// save used region below of arenaHi
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memcpy(OSGetArenaHi() - 128, 0x81000000, sizeof(DSPInitCode));
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memcpy(0x81000000, DSPInitCode, sizeof(DSPInitCode));
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DCFlushRange(0x81000000, sizeof(DSPInitCode));
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AR_SIZE = 0x0043;
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AIDCR = 0x0800 | AIDCR_DSPINT | AIDCR_ARINT | AIDCR_AIINT | AIDCR_HALT;
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// reset DSP and wait
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AIDCR |= AIDCR_RES;
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while(AIDCR & AIDCR_RES);
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// write 0 and wait mail delivery
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DSP_OUTMBOXH = 0;
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while(((DSP_INMBOXH << 16) | DSP_INMBOXL) & 0x80000000);
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// send DSP initialization ucode to ARAM at offset 0
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AR_DMA_MMADDR = OSCachedToPhysical(0x81000000);
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AR_DMA_ARADDR = 0;
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AR_DMA_CNT = 32; // Actually 32 * 4 bytes
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// wait DMA complete
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u16 old = AIDCR; // keep AIDCR_DSPDMA
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while(AIDCR & AIDCR_DSPDMA);
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AIDCR = old; // clear DMA status
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// wait a little
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OSTick old = OSGetTick();
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while((OSGetTick() - old) < 2194);
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// send DSP initialization ucode to ARAM at offset 0 (again)
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AR_DMA_MMADDR = OSCachedToPhysical(0x81000000);
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AR_DMA_ARADDR = 0;
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AR_DMA_CNT = 32; // Actually 32 * 4 bytes
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// wait DMA complete
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u16 old = AIDCR; // keep AIDCR_DSPDMA
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while(AIDCR & AIDCR_DSPDMA);
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AIDCR = old; // clear DMA status
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AIDCR &= ~0x0800
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while(AIDCR & 0x0400);
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AIDCR &= ~AIDCR_HALT;
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while((DSP_INMBOXH & 0x8000) == 0);
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u16 dummy = DSP_INMBOXL; // read nowhere
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AIDCR |= AIDCR_HALT;
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AIDCR = 0x0800 | AIDCR_DSPINT | AIDCR_ARINT | AIDCR_AIINT | AIDCR_HALT;
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// reset DSP and wait
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AIDCR |= AIDCR_RES;
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while(AIDCR & AIDCR_RES);
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// restore saved region
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memcpy(0x81000000, OSGetArenaHi() - 128, sizeof(DSPInitCode));
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}
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