ppsspp/Core/MIPS/ARM
2015-10-10 11:56:59 +02:00
..
ArmAsm.cpp ARM64 typo fix. Add a couple of worrying comments... 2015-10-10 11:56:59 +02:00
ArmCompALU.cpp Avoid any possible shifts by 32. 2015-07-19 13:25:50 -07:00
ArmCompBranch.cpp Add timing for all the basics. 2015-07-03 12:05:08 -07:00
ArmCompFPU.cpp jit: Normalize CONDITIONAL_DISABLE formatting. 2015-07-02 20:31:37 -07:00
ArmCompLoadStore.cpp ARM64: Fix joining of lwl/lwr and swl/swr. "implement" the cache instruction. 2015-07-11 16:25:22 +02:00
ArmCompReplace.cpp Rename the ARM Jit class to ArmJit 2014-12-07 14:25:22 +01:00
ArmCompVFPU.cpp ARM32 JIT: Implement vs2i, vus2i, vc2i (but not vuc2i) 2015-07-11 00:37:57 +02:00
ArmCompVFPUNEON.cpp jit: Normalize CONDITIONAL_DISABLE formatting. 2015-07-02 20:31:37 -07:00
ArmCompVFPUNEONUtil.cpp jit: Normalize CONDITIONAL_DISABLE formatting. 2015-07-02 20:31:37 -07:00
ArmCompVFPUNEONUtil.h Namespacing cleanup (it's bad to do "using namespace" in a header) 2014-12-07 14:44:15 +01:00
ArmJit.cpp Minor fixes, mostly comments 2015-10-10 10:03:34 +02:00
ArmJit.h Pregenerate code to handle rounding mode switches. This time, for all three cores. 2015-10-08 19:58:37 +02:00
ArmRegCache.cpp arm64: Oops, fix flushing zero from an armreg. 2015-07-05 11:57:18 -07:00
ArmRegCache.h arm64: Meld LO and HI together for multiplies. 2015-07-02 20:31:37 -07:00
ArmRegCacheFPU.cpp Unify JitOptions across the backends. 2015-04-12 11:41:26 -07:00
ArmRegCacheFPU.h Unify JitOptions across the backends. 2015-04-12 11:41:26 -07:00