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IRAnalysis.cpp
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Buildfix for VS2017
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2023-08-06 15:06:54 +03:00 |
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IRAnalysis.h
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riscv: Spill registers more intelligently.
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2023-07-30 14:24:12 -07:00 |
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IRAsm.cpp
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Remove most instances of base/logging.h from Common, Core, GPU, more
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2020-08-15 19:08:44 +02:00 |
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IRCompALU.cpp
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irjit: Fix unordered float compares.
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2022-10-30 21:12:59 -07:00 |
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IRCompBranch.cpp
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riscv: Reduce bloat in jit fallbacks.
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2023-07-25 19:42:04 -07:00 |
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IRCompFPU.cpp
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irjit: ZeroFpCond -> FpCondFromReg.
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2023-08-13 10:40:47 -07:00 |
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IRCompLoadStore.cpp
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irjit: Implement ll/sc.
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2023-07-29 17:57:44 -07:00 |
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IRCompVFPU.cpp
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Merge pull request #17875 from unknownbrackets/riscv-jit
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2023-08-09 09:30:15 +02:00 |
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IRFrontend.cpp
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Core: Cleanup disasm buffer usage.
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2023-04-29 09:07:25 -07:00 |
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IRFrontend.h
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irjit: Allow Vec4 to be used with masks.
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2023-08-06 13:46:24 -07:00 |
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IRInst.cpp
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irjit: ZeroFpCond -> FpCondFromReg.
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2023-08-13 10:40:47 -07:00 |
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IRInst.h
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irjit: ZeroFpCond -> FpCondFromReg.
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2023-08-13 10:40:47 -07:00 |
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IRInterpreter.cpp
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irjit: ZeroFpCond -> FpCondFromReg.
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2023-08-13 10:40:47 -07:00 |
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IRInterpreter.h
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jit: Avoid using mips identifier directly.
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2021-02-26 07:24:58 -08:00 |
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IRJit.cpp
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riscv: Spill registers more intelligently.
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2023-07-30 14:24:12 -07:00 |
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IRJit.h
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irjit: Move more to IRNativeBackend, split.
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2023-08-06 00:16:43 -07:00 |
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IRNativeCommon.cpp
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irjit: ZeroFpCond -> FpCondFromReg.
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2023-08-13 10:40:47 -07:00 |
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IRNativeCommon.h
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riscv: Don't cache mipState on backend.
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2023-08-08 23:17:32 -07:00 |
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IRPassSimplify.cpp
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irjit: ZeroFpCond -> FpCondFromReg.
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2023-08-13 10:40:47 -07:00 |
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IRPassSimplify.h
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irjit: Add constructs for validing mem access.
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2022-08-21 13:01:23 -07:00 |
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IRRegCache.cpp
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irjit: Rename IRRegCache to IRImmRegCache.
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2023-08-08 23:05:14 -07:00 |
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IRRegCache.h
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irjit: Rename IRRegCache to IRImmRegCache.
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2023-08-08 23:05:14 -07:00 |
