mirror of
https://github.com/hrydgard/ppsspp.git
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466 lines
12 KiB
C++
466 lines
12 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#if PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
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#include "Core/MemMap.h"
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#include "Core/MIPS/MIPSAnalyst.h"
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#include "Core/Config.h"
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#include "Core/MIPS/MIPSCodeUtils.h"
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#include "Core/MIPS/x86/Jit.h"
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#include "Core/MIPS/x86/RegCache.h"
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#define _RS MIPS_GET_RS(op)
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#define _RT MIPS_GET_RT(op)
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#define _RD MIPS_GET_RD(op)
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#define _FS MIPS_GET_FS(op)
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#define _FT MIPS_GET_FT(op)
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#define _FD MIPS_GET_FD(op)
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#define _SA MIPS_GET_SA(op)
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#define _POS ((op>> 6) & 0x1F)
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#define _SIZE ((op>>11) & 0x1F)
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#define _IMM16 (signed short)(op & 0xFFFF)
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#define _IMM26 (op & 0x03FFFFFF)
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// All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly.
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// Currently known non working ones should have DISABLE.
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// #define CONDITIONAL_DISABLE(flag) { Comp_Generic(op); return; }
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#define CONDITIONAL_DISABLE(flag) if (jo.Disabled(JitDisable::flag)) { Comp_Generic(op); return; }
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#define DISABLE { Comp_Generic(op); return; }
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#define INVALIDOP { Comp_Generic(op); return; }
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namespace MIPSComp {
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using namespace Gen;
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void Jit::CompITypeMemRead(MIPSOpcode op, u32 bits, void (XEmitter::*mov)(int, int, X64Reg, OpArg), const void *safeFunc)
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{
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CONDITIONAL_DISABLE(LSU);
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int offset = _IMM16;
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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gpr.Lock(rt, rs);
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gpr.MapReg(rt, rt == rs, true);
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JitSafeMem safe(this, rs, offset);
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OpArg src;
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if (safe.PrepareRead(src, bits / 8))
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(this->*mov)(32, bits, gpr.RX(rt), src);
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if (safe.PrepareSlowRead(safeFunc))
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(this->*mov)(32, bits, gpr.RX(rt), R(EAX));
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safe.Finish();
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gpr.UnlockAll();
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}
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static OpArg DowncastImm(OpArg in, int bits) {
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if (!in.IsImm())
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return in;
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if (in.GetImmBits() > bits) {
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in.SetImmBits(bits);
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return in;
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}
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return in;
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}
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void Jit::CompITypeMemWrite(MIPSOpcode op, u32 bits, const void *safeFunc, bool makeRTWritable)
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{
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CONDITIONAL_DISABLE(LSU);
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int offset = _IMM16;
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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gpr.Lock(rt, rs);
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if (rt == MIPS_REG_ZERO || gpr.R(rt).IsImm()) {
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if (makeRTWritable) {
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gpr.MapReg(rt, true, true);
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}
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// NOTICE_LOG(JIT, "%d-bit Imm at %08x : %08x", bits, js.blockStart, (u32)gpr.R(rt).GetImmValue());
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} else {
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gpr.MapReg(rt, true, false);
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}
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#if PPSSPP_ARCH(X86)
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// We use EDX so we can have DL for 8-bit ops.
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const bool needSwap = bits == 8 && !gpr.R(rt).IsSimpleReg(EDX) && !gpr.R(rt).IsSimpleReg(ECX);
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if (needSwap)
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gpr.FlushLockX(EDX);
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#else
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const bool needSwap = false;
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#endif
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JitSafeMem safe(this, rs, offset);
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OpArg dest;
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if (safe.PrepareWrite(dest, bits / 8))
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{
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if (needSwap)
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{
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MOV(32, R(EDX), gpr.R(rt));
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MOV(bits, dest, R(EDX));
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}
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else {
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if (rt == MIPS_REG_ZERO) {
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switch (bits) {
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case 8: MOV(8, dest, Imm8(0)); break;
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case 16: MOV(16, dest, Imm16(0)); break;
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case 32: MOV(32, dest, Imm32(0)); break;
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}
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} else {
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// The downcast is needed so we don't try to generate a 8-bit write with a 32-bit imm
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// (that might have been generated from an li instruction) which is illegal.
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MOV(bits, dest, DowncastImm(gpr.R(rt), bits));
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}
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}
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}
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if (safe.PrepareSlowWrite())
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safe.DoSlowWrite(safeFunc, gpr.R(rt));
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safe.Finish();
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if (needSwap)
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gpr.UnlockAllX();
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gpr.UnlockAll();
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}
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void Jit::CompITypeMemUnpairedLR(MIPSOpcode op, bool isStore)
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{
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CONDITIONAL_DISABLE(LSU);
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int offset = _IMM16;
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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X64Reg shiftReg = ECX;
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gpr.FlushLockX(ECX, EDX);
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#if PPSSPP_ARCH(AMD64)
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// On x64, we need ECX for CL, but it's also the first arg and gets lost. Annoying.
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gpr.FlushLockX(R9);
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shiftReg = R9;
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#endif
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gpr.Lock(rt, rs);
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gpr.MapReg(rt, true, !isStore);
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// Grab the offset from alignment for shifting (<< 3 for bytes -> bits.)
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MOV(32, R(shiftReg), gpr.R(rs));
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ADD(32, R(shiftReg), Imm32(offset));
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AND(32, R(shiftReg), Imm32(3));
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SHL(32, R(shiftReg), Imm8(3));
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{
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JitSafeMem safe(this, rs, offset, ~3);
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OpArg src;
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if (safe.PrepareRead(src, 4))
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{
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if (!src.IsSimpleReg(EAX))
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MOV(32, R(EAX), src);
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CompITypeMemUnpairedLRInner(op, shiftReg);
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}
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if (safe.PrepareSlowRead(safeMemFuncs.readU32))
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CompITypeMemUnpairedLRInner(op, shiftReg);
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safe.Finish();
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}
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// For store ops, write EDX back to memory.
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if (isStore)
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{
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JitSafeMem safe(this, rs, offset, ~3);
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OpArg dest;
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if (safe.PrepareWrite(dest, 4))
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MOV(32, dest, R(EDX));
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if (safe.PrepareSlowWrite())
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safe.DoSlowWrite(safeMemFuncs.writeU32, R(EDX));
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safe.Finish();
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}
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gpr.UnlockAll();
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gpr.UnlockAllX();
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}
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void Jit::CompITypeMemUnpairedLRInner(MIPSOpcode op, X64Reg shiftReg)
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{
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CONDITIONAL_DISABLE(LSU);
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int o = op>>26;
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MIPSGPReg rt = _RT;
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// Make sure we have the shift for the target in ECX.
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if (shiftReg != ECX)
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MOV(32, R(ECX), R(shiftReg));
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// Now use that shift (left on target, right on source.)
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switch (o)
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{
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case 34: //lwl
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MOV(32, R(EDX), Imm32(0x00ffffff));
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SHR(32, R(EDX), R(CL));
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AND(32, gpr.R(rt), R(EDX));
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break;
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case 38: //lwr
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SHR(32, R(EAX), R(CL));
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break;
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case 42: //swl
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MOV(32, R(EDX), Imm32(0xffffff00));
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SHL(32, R(EDX), R(CL));
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AND(32, R(EAX), R(EDX));
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break;
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case 46: //swr
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MOV(32, R(EDX), gpr.R(rt));
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SHL(32, R(EDX), R(CL));
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// EDX is already the target value to write, but may be overwritten below. Save it.
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PUSH(EDX);
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break;
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default:
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_dbg_assert_msg_(false, "Unsupported left/right load/store instruction.");
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}
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// Flip ECX around from 3 bytes / 24 bits.
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if (shiftReg == ECX)
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{
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MOV(32, R(EDX), Imm32(24));
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SUB(32, R(EDX), R(ECX));
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MOV(32, R(ECX), R(EDX));
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}
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else
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{
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MOV(32, R(ECX), Imm32(24));
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SUB(32, R(ECX), R(shiftReg));
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}
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// Use the flipped shift (left on source, right on target) and write target.
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switch (o)
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{
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case 34: //lwl
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SHL(32, R(EAX), R(CL));
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OR(32, gpr.R(rt), R(EAX));
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break;
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case 38: //lwr
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MOV(32, R(EDX), Imm32(0xffffff00));
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SHL(32, R(EDX), R(CL));
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AND(32, gpr.R(rt), R(EDX));
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OR(32, gpr.R(rt), R(EAX));
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break;
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case 42: //swl
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MOV(32, R(EDX), gpr.R(rt));
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SHR(32, R(EDX), R(CL));
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OR(32, R(EDX), R(EAX));
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break;
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case 46: //swr
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MOV(32, R(EDX), Imm32(0x00ffffff));
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SHR(32, R(EDX), R(CL));
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AND(32, R(EAX), R(EDX));
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// This is the target value we saved earlier.
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POP(EDX);
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OR(32, R(EDX), R(EAX));
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break;
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default:
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_dbg_assert_msg_(false, "Unsupported left/right load/store instruction.");
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}
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}
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void Jit::Comp_ITypeMem(MIPSOpcode op)
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{
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CONDITIONAL_DISABLE(LSU);
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int offset = _IMM16;
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MIPSGPReg rs = _RS;
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MIPSGPReg rt = _RT;
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int o = op>>26;
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if (((op >> 29) & 1) == 0 && rt == MIPS_REG_ZERO) {
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// Don't load anything into $zr
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return;
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}
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CheckMemoryBreakpoint(0, rs, offset);
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switch (o)
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{
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case 37: //R(rt) = ReadMem16(addr); break; //lhu
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CompITypeMemRead(op, 16, &XEmitter::MOVZX, safeMemFuncs.readU16);
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break;
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case 36: //R(rt) = ReadMem8 (addr); break; //lbu
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CompITypeMemRead(op, 8, &XEmitter::MOVZX, safeMemFuncs.readU8);
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break;
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case 35: //R(rt) = ReadMem32(addr); break; //lw
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CompITypeMemRead(op, 32, &XEmitter::MOVZX, safeMemFuncs.readU32);
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break;
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case 32: //R(rt) = SignExtend8ToU32 (ReadMem8 (addr)); break; //lb
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CompITypeMemRead(op, 8, &XEmitter::MOVSX, safeMemFuncs.readU8);
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break;
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case 33: //R(rt) = SignExtend16ToU32(ReadMem16(addr)); break; //lh
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CompITypeMemRead(op, 16, &XEmitter::MOVSX, safeMemFuncs.readU16);
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break;
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case 40: //WriteMem8 (addr, R(rt)); break; //sb
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CompITypeMemWrite(op, 8, safeMemFuncs.writeU8);
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break;
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case 41: //WriteMem16(addr, R(rt)); break; //sh
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CompITypeMemWrite(op, 16, safeMemFuncs.writeU16);
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break;
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case 43: //WriteMem32(addr, R(rt)); break; //sw
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CompITypeMemWrite(op, 32, safeMemFuncs.writeU32);
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break;
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case 34: //lwl
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{
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MIPSOpcode nextOp = GetOffsetInstruction(1);
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// Looking for lwr rd, offset-3(rs) which makes a pair.
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u32 desiredOp = ((op & 0xFFFF0000) + (4 << 26)) + (offset - 3);
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if (!js.inDelaySlot && nextOp == desiredOp && !jo.Disabled(JitDisable::LSU_UNALIGNED))
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{
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CheckMemoryBreakpoint(1, rs, offset - 3);
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EatInstruction(nextOp);
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// nextOp has the correct address.
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CompITypeMemRead(nextOp, 32, &XEmitter::MOVZX, safeMemFuncs.readU32);
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}
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else
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CompITypeMemUnpairedLR(op, false);
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}
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break;
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case 38: //lwr
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{
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MIPSOpcode nextOp = GetOffsetInstruction(1);
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// Looking for lwl rd, offset+3(rs) which makes a pair.
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u32 desiredOp = ((op & 0xFFFF0000) - (4 << 26)) + (offset + 3);
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if (!js.inDelaySlot && nextOp == desiredOp && !jo.Disabled(JitDisable::LSU_UNALIGNED))
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{
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CheckMemoryBreakpoint(1, rs, offset + 3);
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EatInstruction(nextOp);
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// op has the correct address.
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CompITypeMemRead(op, 32, &XEmitter::MOVZX, safeMemFuncs.readU32);
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}
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else
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CompITypeMemUnpairedLR(op, false);
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}
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break;
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case 42: //swl
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{
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MIPSOpcode nextOp = GetOffsetInstruction(1);
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// Looking for swr rd, offset-3(rs) which makes a pair.
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u32 desiredOp = ((op & 0xFFFF0000) + (4 << 26)) + (offset - 3);
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if (!js.inDelaySlot && nextOp == desiredOp && !jo.Disabled(JitDisable::LSU_UNALIGNED))
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{
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CheckMemoryBreakpoint(1, rs, offset - 3);
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EatInstruction(nextOp);
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// nextOp has the correct address.
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CompITypeMemWrite(nextOp, 32, safeMemFuncs.writeU32);
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}
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else
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CompITypeMemUnpairedLR(op, true);
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}
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break;
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case 46: //swr
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{
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MIPSOpcode nextOp = GetOffsetInstruction(1);
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// Looking for swl rd, offset+3(rs) which makes a pair.
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u32 desiredOp = ((op & 0xFFFF0000) - (4 << 26)) + (offset + 3);
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if (!js.inDelaySlot && nextOp == desiredOp && !jo.Disabled(JitDisable::LSU_UNALIGNED))
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{
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CheckMemoryBreakpoint(1, rs, offset + 3);
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EatInstruction(nextOp);
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// op has the correct address.
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CompITypeMemWrite(op, 32, safeMemFuncs.writeU32);
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}
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else
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CompITypeMemUnpairedLR(op, true);
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}
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break;
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default:
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Comp_Generic(op);
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return;
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}
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}
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void Jit::Comp_StoreSync(MIPSOpcode op) {
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CONDITIONAL_DISABLE(LSU);
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int offset = _IMM16;
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MIPSGPReg rt = _RT;
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MIPSGPReg rs = _RS;
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// Note: still does something even if loading to zero.
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CheckMemoryBreakpoint(0, rs, offset);
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FixupBranch skipStore;
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FixupBranch finish;
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switch (op >> 26) {
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case 48: // ll
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CompITypeMemRead(op, 32, &XEmitter::MOVZX, safeMemFuncs.readU32);
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MOV(8, MDisp(X64JitConstants::CTXREG, -128 + offsetof(MIPSState, llBit)), Imm8(1));
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break;
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case 56: // sc
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CMP(8, MDisp(X64JitConstants::CTXREG, -128 + offsetof(MIPSState, llBit)), Imm8(1));
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skipStore = J_CC(CC_NE);
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CompITypeMemWrite(op, 32, safeMemFuncs.writeU32, true);
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MOV(32, gpr.R(rt), Imm32(1));
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finish = J();
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SetJumpTarget(skipStore);
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MOV(32, gpr.R(rt), Imm32(0));
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SetJumpTarget(finish);
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break;
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default:
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INVALIDOP;
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}
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}
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void Jit::Comp_Cache(MIPSOpcode op) {
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CONDITIONAL_DISABLE(LSU);
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int func = (op >> 16) & 0x1F;
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// See Int_Cache for the definitions.
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switch (func) {
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case 24: break;
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case 25: break;
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case 27: break;
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case 30: break;
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default:
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// Fall back to the interpreter.
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DISABLE;
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}
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}
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}
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#endif // PPSSPP_ARCH(X86) || PPSSPP_ARCH(AMD64)
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