mirror of
https://github.com/hrydgard/ppsspp.git
synced 2025-04-02 11:01:50 -04:00
313 lines
8.3 KiB
C++
313 lines
8.3 KiB
C++
// Copyright (c) 2012- PPSSPP Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0 or later versions.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official git repository and contact information can be found at
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#pragma once
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#include "../../../Globals.h"
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#include "Core/MIPS/JitCommon/JitBlockCache.h"
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#include "Core/MIPS/ARM/ArmRegCache.h"
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#include "Core/MIPS/ARM/ArmRegCacheFPU.h"
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#include "Core/MIPS/ARM/ArmAsm.h"
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#if defined(MAEMO)
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#include "stddef.h"
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#endif
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namespace MIPSComp
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{
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struct ArmJitOptions
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{
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ArmJitOptions()
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{
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enableBlocklink = true;
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downcountInRegister = true;
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}
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bool enableBlocklink;
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bool downcountInRegister;
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};
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struct ArmJitState
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{
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enum PrefixState
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{
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PREFIX_UNKNOWN = 0x00,
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PREFIX_KNOWN = 0x01,
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PREFIX_DIRTY = 0x10,
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PREFIX_KNOWN_DIRTY = 0x11,
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};
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u32 compilerPC;
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u32 blockStart;
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int nextExit;
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bool cancel;
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bool inDelaySlot;
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int downcountAmount;
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bool compiling; // TODO: get rid of this in favor of using analysis results to determine end of block
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JitBlock *curBlock;
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// VFPU prefix magic
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bool startDefaultPrefix;
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u32 prefixS;
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u32 prefixT;
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u32 prefixD;
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PrefixState prefixSFlag;
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PrefixState prefixTFlag;
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PrefixState prefixDFlag;
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void PrefixStart() {
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if (startDefaultPrefix) {
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EatPrefix();
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} else {
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PrefixUnknown();
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}
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}
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void PrefixUnknown() {
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prefixSFlag = PREFIX_UNKNOWN;
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prefixTFlag = PREFIX_UNKNOWN;
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prefixDFlag = PREFIX_UNKNOWN;
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}
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bool MayHavePrefix() const {
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if (HasUnknownPrefix()) {
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return true;
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} else if (prefixS != 0xE4 || prefixT != 0xE4 || prefixD != 0) {
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return true;
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} else if (VfpuWriteMask() != 0) {
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return true;
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}
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return false;
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}
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bool HasUnknownPrefix() const {
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if (!(prefixSFlag & PREFIX_KNOWN) || !(prefixTFlag & PREFIX_KNOWN) || !(prefixDFlag & PREFIX_KNOWN)) {
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return true;
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}
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return false;
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}
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bool HasNoPrefix() const {
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return (prefixDFlag & PREFIX_KNOWN) && (prefixSFlag & PREFIX_KNOWN) && (prefixTFlag & PREFIX_KNOWN) && (prefixS == 0xE4 && prefixT == 0xE4 && prefixD == 0);
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}
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void EatPrefix() {
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if ((prefixSFlag & PREFIX_KNOWN) == 0 || prefixS != 0xE4) {
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prefixSFlag = PREFIX_KNOWN_DIRTY;
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prefixS = 0xE4;
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}
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if ((prefixTFlag & PREFIX_KNOWN) == 0 || prefixT != 0xE4) {
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prefixTFlag = PREFIX_KNOWN_DIRTY;
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prefixT = 0xE4;
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}
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if ((prefixDFlag & PREFIX_KNOWN) == 0 || prefixD != 0x0 || VfpuWriteMask() != 0) {
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prefixDFlag = PREFIX_KNOWN_DIRTY;
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prefixD = 0x0;
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}
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}
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u8 VfpuWriteMask() const {
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_assert_(prefixDFlag & PREFIX_KNOWN);
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return (prefixD >> 8) & 0xF;
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}
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bool VfpuWriteMask(int i) const {
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_assert_(prefixDFlag & PREFIX_KNOWN);
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return (prefixD >> (8 + i)) & 1;
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}
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};
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enum CompileDelaySlotFlags
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{
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// Easy, nothing extra.
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DELAYSLOT_NICE = 0,
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// Flush registers after delay slot.
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DELAYSLOT_FLUSH = 1,
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// Preserve flags.
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DELAYSLOT_SAFE = 2,
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// Flush registers after and preserve flags.
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DELAYSLOT_SAFE_FLUSH = DELAYSLOT_FLUSH | DELAYSLOT_SAFE,
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};
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class Jit : public ArmGen::ARMXCodeBlock
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{
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public:
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Jit(MIPSState *mips);
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void DoState(PointerWrap &p);
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static void DoDummyState(PointerWrap &p);
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// Compiled ops should ignore delay slots
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// the compiler will take care of them by itself
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// OR NOT
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void Comp_Generic(MIPSOpcode op);
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void RunLoopUntil(u64 globalticks);
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void Compile(u32 em_address); // Compiles a block at current MIPS PC
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const u8 *DoJit(u32 em_address, JitBlock *b);
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void CompileDelaySlot(int flags);
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void CompileAt(u32 addr);
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void EatInstruction(MIPSOpcode op);
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void Comp_RunBlock(MIPSOpcode op);
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// Ops
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void Comp_ITypeMem(MIPSOpcode op);
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void Comp_RelBranch(MIPSOpcode op);
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void Comp_RelBranchRI(MIPSOpcode op);
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void Comp_FPUBranch(MIPSOpcode op);
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void Comp_FPULS(MIPSOpcode op);
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void Comp_FPUComp(MIPSOpcode op);
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void Comp_Jump(MIPSOpcode op);
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void Comp_JumpReg(MIPSOpcode op);
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void Comp_Syscall(MIPSOpcode op);
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void Comp_Break(MIPSOpcode op);
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void Comp_IType(MIPSOpcode op);
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void Comp_RType2(MIPSOpcode op);
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void Comp_RType3(MIPSOpcode op);
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void Comp_ShiftType(MIPSOpcode op);
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void Comp_Allegrex(MIPSOpcode op);
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void Comp_Allegrex2(MIPSOpcode op);
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void Comp_VBranch(MIPSOpcode op);
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void Comp_MulDivType(MIPSOpcode op);
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void Comp_Special3(MIPSOpcode op);
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void Comp_FPU3op(MIPSOpcode op);
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void Comp_FPU2op(MIPSOpcode op);
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void Comp_mxc1(MIPSOpcode op);
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void Comp_DoNothing(MIPSOpcode op);
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void Comp_SV(MIPSOpcode op);
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void Comp_SVQ(MIPSOpcode op);
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void Comp_VPFX(MIPSOpcode op);
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void Comp_VVectorInit(MIPSOpcode op);
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void Comp_VMatrixInit(MIPSOpcode op);
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void Comp_VDot(MIPSOpcode op);
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void Comp_VecDo3(MIPSOpcode op);
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void Comp_VV2Op(MIPSOpcode op);
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void Comp_Mftv(MIPSOpcode op);
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void Comp_Vmtvc(MIPSOpcode op);
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void Comp_Vmmov(MIPSOpcode op);
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void Comp_VScl(MIPSOpcode op);
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void Comp_Vmmul(MIPSOpcode op);
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void Comp_Vmscl(MIPSOpcode op);
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void Comp_Vtfm(MIPSOpcode op);
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void Comp_VHdp(MIPSOpcode op);
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void Comp_VCrs(MIPSOpcode op);
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void Comp_VDet(MIPSOpcode op);
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void Comp_Vi2x(MIPSOpcode op);
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void Comp_Vx2i(MIPSOpcode op);
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void Comp_Vf2i(MIPSOpcode op);
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void Comp_Vi2f(MIPSOpcode op);
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void Comp_Vcst(MIPSOpcode op);
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void Comp_Vhoriz(MIPSOpcode op);
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void Comp_VRot(MIPSOpcode op);
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void Comp_VIdt(MIPSOpcode op);
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void Comp_Vcmp(MIPSOpcode op);
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void Comp_Vcmov(MIPSOpcode op);
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void Comp_Viim(MIPSOpcode op);
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void Comp_Vfim(MIPSOpcode op);
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void Comp_VCrossQuat(MIPSOpcode op);
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void Comp_Vsge(MIPSOpcode op);
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void Comp_Vslt(MIPSOpcode op);
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JitBlockCache *GetBlockCache() { return &blocks; }
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void ClearCache();
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void ClearCacheAt(u32 em_address, int length = 4);
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void EatPrefix() { js.EatPrefix(); }
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private:
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void GenerateFixedCode();
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void FlushAll();
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void FlushPrefixV();
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void WriteDownCount(int offset = 0);
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void MovFromPC(ARMReg r);
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void MovToPC(ARMReg r);
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void SaveDowncount();
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void RestoreDowncount();
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void WriteExit(u32 destination, int exit_num);
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void WriteExitDestInR(ARMReg Reg);
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void WriteSyscallExit();
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// Utility compilation functions
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void BranchFPFlag(MIPSOpcode op, ArmGen::CCFlags cc, bool likely);
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void BranchVFPUFlag(MIPSOpcode op, ArmGen::CCFlags cc, bool likely);
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void BranchRSZeroComp(MIPSOpcode op, ArmGen::CCFlags cc, bool andLink, bool likely);
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void BranchRSRTComp(MIPSOpcode op, ArmGen::CCFlags cc, bool likely);
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// Utilities to reduce duplicated code
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void CompImmLogic(int rs, int rt, u32 uimm, void (ARMXEmitter::*arith)(ARMReg dst, ARMReg src, Operand2 op2), u32 (*eval)(u32 a, u32 b));
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void CompType3(int rd, int rs, int rt, void (ARMXEmitter::*arithOp2)(ARMReg dst, ARMReg rm, Operand2 rn), u32 (*eval)(u32 a, u32 b), bool isSub = false);
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void CompShiftImm(MIPSOpcode op, ArmGen::ShiftType shiftType);
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void CompShiftVar(MIPSOpcode op, ArmGen::ShiftType shiftType);
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void ApplyPrefixST(u8 *vregs, u32 prefix, VectorSize sz);
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void ApplyPrefixD(const u8 *vregs, VectorSize sz);
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void GetVectorRegsPrefixS(u8 *regs, VectorSize sz, int vectorReg) {
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_assert_(js.prefixSFlag & ArmJitState::PREFIX_KNOWN);
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GetVectorRegs(regs, sz, vectorReg);
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ApplyPrefixST(regs, js.prefixS, sz);
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}
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void GetVectorRegsPrefixT(u8 *regs, VectorSize sz, int vectorReg) {
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_assert_(js.prefixTFlag & ArmJitState::PREFIX_KNOWN);
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GetVectorRegs(regs, sz, vectorReg);
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ApplyPrefixST(regs, js.prefixT, sz);
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}
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void GetVectorRegsPrefixD(u8 *regs, VectorSize sz, int vectorReg);
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// Utils
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void SetR0ToEffectiveAddress(int rs, s16 offset);
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void SetCCAndR0ForSafeAddress(int rs, s16 offset, ARMReg tempReg);
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JitBlockCache blocks;
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ArmJitOptions jo;
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ArmJitState js;
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ArmRegCache gpr;
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ArmRegCacheFPU fpr;
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MIPSState *mips_;
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int dontLogBlocks;
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int logBlocks;
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public:
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// Code pointers
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const u8 *enterCode;
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const u8 *outerLoop;
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const u8 *outerLoopPCInR0;
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const u8 *dispatcherCheckCoreState;
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const u8 *dispatcherPCInR0;
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const u8 *dispatcher;
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const u8 *dispatcherNoCheck;
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const u8 *breakpointBailout;
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};
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typedef void (Jit::*MIPSCompileFunc)(MIPSOpcode opcode);
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} // namespace MIPSComp
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