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Just invalidate blocks on ClearCacheAt().

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This makes it safe to call from a jitted syscall, etc.
This commit is contained in:
Unknown W. Brackets 2013-09-01 00:21:41 -07:00
parent 14bcca1f53
commit b558189c37
8 changed files with 14 additions and 14 deletions
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3
Core/Debugger/Breakpoints.cpp
View file

@ -298,8 +298,9 @@ void CBreakPoints::Update(u32 addr)
{
if (MIPSComp::jit && Core_IsInactive())
{
// In case this is a delay slot, clear the previous instruction too.
if (addr != 0)
MIPSComp::jit->ClearCacheAt(addr);
MIPSComp::jit->ClearCacheAt(addr - 4, 8);
else
MIPSComp::jit->ClearCache();
}

5
Core/MIPS/ARM/ArmJit.cpp
View file

@ -118,10 +118,9 @@ void Jit::ClearCache()
GenerateFixedCode();
}
void Jit::ClearCacheAt(u32 em_address)
void Jit::ClearCacheAt(u32 em_address, int length)
{
// TODO: Properly.
ClearCache();
blocks.InvalidateICache(em_address, length);
}
void Jit::CompileAt(u32 addr)

2
Core/MIPS/ARM/ArmJit.h
View file

@ -230,7 +230,7 @@ public:
JitBlockCache *GetBlockCache() { return &blocks; }
void ClearCache();
void ClearCacheAt(u32 em_address);
void ClearCacheAt(u32 em_address, int length = 4);
void EatPrefix() { js.EatPrefix(); }

4
Core/MIPS/PPC/PpcJit.cpp
View file

@ -169,8 +169,8 @@ void Jit::ClearCache() {
GenerateFixedCode();
}
void Jit::ClearCacheAt(u32 em_address) {
ClearCache();
void Jit::ClearCacheAt(u32 em_address, int length) {
blocks.InvalidateICache(em_address, length);
}
Jit::Jit(MIPSState *mips) : blocks(mips, this), gpr(mips, &jo),mips_(mips)

2
Core/MIPS/PPC/PpcJit.h
View file

@ -242,7 +242,7 @@ namespace MIPSComp
void WriteSyscallExit();
void ClearCache();
void ClearCacheAt(u32 em_address);
void ClearCacheAt(u32 em_address, int length = 4);
void RunLoopUntil(u64 globalticks);
void GenerateFixedCode();

5
Core/MIPS/x86/Jit.cpp
View file

@ -188,10 +188,9 @@ void Jit::ClearCache()
ClearCodeSpace();
}
void Jit::ClearCacheAt(u32 em_address)
void Jit::ClearCacheAt(u32 em_address, int length)
{
// TODO: Properly.
ClearCache();
blocks.InvalidateICache(em_address, length);
}
void Jit::CompileDelaySlot(int flags, RegCacheState *state)

2
Core/MIPS/x86/Jit.h
View file

@ -266,7 +266,7 @@ public:
AsmRoutineManager &Asm() { return asm_; }
void ClearCache();
void ClearCacheAt(u32 em_address);
void ClearCacheAt(u32 em_address, int length = 4);
private:
void GetStateAndFlushAll(RegCacheState &state);
void RestoreState(const RegCacheState state);

5
Windows/Debugger/CtrlDisAsmView.cpp
View file

@ -308,9 +308,10 @@ void CtrlDisAsmView::assembleOpcode(u32 address, std::string defaultText)
result = MIPSAsm::MipsAssembleOpcode(op.c_str(),debugger,address,encoded);
if (result == true)
{
Memory::Write_U32(encoded,address);
Memory::Write_U32(encoded, address);
// In case this is a delay slot or combined instruction, clear cache above it too.
if (MIPSComp::jit)
MIPSComp::jit->ClearCacheAt(address);
MIPSComp::jit->ClearCacheAt(address - 4, 8);
redraw();
} else {
MessageBox(wnd,L"Couldn't assemble.",L"Error",MB_OK);