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8858 commits

Author SHA1 Message Date
Henrik Rydgård
42f2312030 Remove the old CPU threading remains, start redesigning interfaces. 2018-01-27 15:10:17 +01:00
Henrik Rydgård
34f79904fd IR: This optimization is safe when all three regs are consecutive, so avoid disabling it unnecessarily. 2018-01-10 09:19:27 +01:00
Henrik Rydgård
fb0e81484b Minor cleanup 2018-01-10 09:19:27 +01:00
Henrik Rydgård
4a32ec3102
Merge pull request #10516 from unknownbrackets/irjit-lwr 
irjit: Optimize out more temps and lwl/lwr operations
 2018-01-10 09:11:10 +01:00
Unknown W. Brackets
b6bb0159e3 irjit: Remove Comp_ITypeMemLR. 2018-01-09 18:06:25 -08:00
Unknown W. Brackets
f01e06aefd irjit: Improve multiple lwr in a row. 2018-01-07 21:06:02 -08:00
Unknown W. Brackets
fbeedd333b irjit: Swap moves when it may allow clobbering. 
Example:
addiu a0, a1, a2
mov s0, a0
addiu a0, a2, a3

By swapping the mov, we can eliminate it.

Only going one back because it's common and didn't want to track reads.
 2018-01-07 21:06:02 -08:00
Unknown W. Brackets
d27e428659 irjit: Convert lwr and friends to easier code. 
This makes it easier to write a (working) jit backend from IR, since these
ops are always annoying to get right.
 2018-01-07 21:06:00 -08:00
Unknown W. Brackets
b11f00cead irjit: Combine lwl/lwr and swl/swr, like before. 
Still want to inline the operation, because the backend shouldn't have to
redo it every time, and we want the temps cleaned up if possible.
 2018-01-07 21:05:58 -08:00
Unknown W. Brackets
c6d690e9b8 irjit: Handle Left/Right ops in passes. 2018-01-07 21:05:57 -08:00
Unknown W. Brackets
6dda053365 irjit: Add dedicated ops for lwl/swl and friends. 
Temporarily removes optimizations.
 2018-01-07 21:05:57 -08:00
Unknown W. Brackets
cd3f4881a5 irjit: Optimize out temp lhs copies. 
Common example:
li v0, 1
beq s2, v0, somewhere
li v0, 2

Which was copying s2 before.  This pattern generally doesn't happen in
MIPS code, though, so really only catches that (very common) case.
 2018-01-07 12:11:16 -08:00
Unknown W. Brackets
97674b80bd irjit: Skip preloading blocks with jump to 0. 
These will be changed before executing anyway.
 2018-01-06 17:23:53 -08:00
Unknown W. Brackets
cc8e9a93c3 irjit: For debug, return the best block at addr. 
Invalidation may result in multiple matching blocks, prefer any that is
currently valid.
 2018-01-06 17:08:54 -08:00
Unknown W. Brackets
463b2a90c7 irjit: Allow precompiling funcs at start. 
This can take a second, but cuts down on jitc spikes throughout runtime.
Note: bits of the game will still be recompiled as games change code.

This is basically the same operation as loading from cache, without the
cache yet.
 2018-01-06 17:06:53 -08:00
Unknown W. Brackets
6149ac584f jit: Add interface to precompile functions. 
This doesn't actually do any preloading yet, it just adds an API.
 2018-01-06 16:43:38 -08:00
Unknown W. Brackets
ccd562d934 irjit: Add a safety check for block num overflow. 
In case a game is very frequently modifying some block.
 2018-01-04 23:24:15 -08:00
Unknown W. Brackets
0bfab27b46 irjit: Calculate bloat statistics. 
At least based on IR for now.  Can do something else later.

memset() was causing a crash on the std::map.
 2018-01-04 23:09:03 -08:00
Henrik Rydgård
2709472abd
Merge pull request #10506 from hrydgard/ir-interpreter-simd 
More IR interpreter SIMD
 2018-01-05 01:21:32 +01:00
Henrik Rydgård
8c3a50d089
Merge pull request #10505 from hrydgard/ir-disasm-jit-compare 
Show IR disassembly in JIT Compare screen
 2018-01-05 01:20:49 +01:00
Henrik Rydgård
d1d01bfdcb Cleanup GetBlockNumberFromStartAddress 2018-01-05 01:20:10 +01:00
Henrik Rydgård
331a8f91e8 Fix that weird unordered compare mode, hopefully 2018-01-04 20:06:26 +01:00
Henrik Rydgård
18be23eccc IR: More fixes. Still something wrong with VFPU compares (not caused by this PR). 2018-01-04 19:38:36 +01:00
Henrik Rydgård
ca9050b84c On Linux, can't even include nmmintrin without explicitly enabling SSE 4.2 support. 2018-01-04 18:27:19 +01:00
Henrik Rydgård
fe88d12055 IR interpreter: Add some braces to allow variable declaration in the switch cases. 2018-01-04 18:27:19 +01:00
Henrik Rydgård
e0cc126d09 Add some more SIMD support to IR interpreter. Mostly just because, but also serves as implementation reference for later code generation backends. 2018-01-04 18:27:19 +01:00
Henrik Rydgård
a128624f98 IRInterpreter: Fix bugs in floating point truncation functions 2018-01-04 18:25:54 +01:00
Henrik Rydgård
1a97f62dc9 Fix running the CPU test from the UI. 2018-01-04 18:10:41 +01:00
Henrik Rydgård
468b830bec Show IR disassembly in JIT Compare screen 2018-01-04 12:23:23 +01:00
Henrik Rydgård
604b3c3e97 IR Interpreter: Add missing break; to switch case IROp::FSign. 2018-01-04 11:08:56 +01:00
Unknown W. Brackets
bc541bd020 irjit: Encode downcount directly as a constant. 
Simpler this way, now.
 2018-01-03 23:32:31 -08:00
Unknown W. Brackets
cffb2d61a7 irjit: Embed constant inside IRInst. 
This simplifies a bunch of code and improves compile performance by about
30%, at the cost of a bit more memory.
 2018-01-03 23:24:04 -08:00
Unknown W. Brackets
64b57a0329 irjit: Fix swr typo. 
Shifting the wrong direction - oops.
 2018-01-03 08:14:25 -08:00
Henrik Rydgård
3ac2350ad6 IR Interpreter: Add a comment, minor cleanup, minor SSE stuff. 2018-01-03 16:31:55 +01:00
Unknown W. Brackets
29ed48c32a Module: Avoid scanning stubs if possible. 
In this case, we often scan some garbage, but let's reduce it at least.
 2018-01-02 22:21:08 -08:00
Unknown W. Brackets
00a05e97ac Module: Scan modules with no sections at all. 
Also, fix some off-by-one issues with end addresses.
 2018-01-02 22:20:09 -08:00
Unknown W. Brackets
30b2d05bac Module: Correct detection of executable sections. 2018-01-02 21:53:13 -08:00
Henrik Rydgård
690a409dac
Merge pull request #10496 from unknownbrackets/cpu-bgstart 
Core: Asynchronously load the main ELF
 2018-01-02 11:31:58 +01:00
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b41413b8a5 Core: Asynchronously load the main ELF. 
Sometimes it takes a little time.  More importantly, this allows us to
load caches or do other things at start that might be a tad slow.

Not doing anything like that yet, though.
 2018-01-01 22:58:06 -08:00
Unknown W. Brackets
b11858d9a0 irjit: Properly account for delay slots in size. 
Otherwise we think blocks are 4 bytes too short, which can affect
invalidation.
 2018-01-01 22:54:40 -08:00
Kentucky Compass
20794081ea iOS: Nix iosCanUseJit and targetIsJailbroken. Move NativeInit call to main so it can take cmd line args. 2018-01-01 19:10:44 -08:00
Henrik Rydgård
263941e9e0
Merge pull request #10494 from unknownbrackets/irjit 
irjit: Implement lwl/etc.
 2018-01-01 19:08:32 +01:00
Unknown W. Brackets
6509f8b433 HLE: Reset latestSyscall on save state load. 
Loading a save state might call functions which call HLE log, such as
AtracSetContext.  This was outputting confusing log / reporting messages
based on a random recent syscall.
 2018-01-01 08:57:08 -08:00
Unknown W. Brackets
3abcc4d6d8 irjit: Implement lwl/lwr/swl/swr. 
This is very similar to the arm64jit implementation.
 2018-01-01 08:38:13 -08:00
Unknown W. Brackets
b37ba9e599 irjit: Add options for compile/optimize steps. 
This way the backend can set flags for the type of IR it wants.  It's
seems too complex to combine certain things like lwl/lwr in a pass.
 2018-01-01 08:38:12 -08:00
Unknown W. Brackets
671be24105 irjit: Add extra temps to make lwl/swl/etc. easier. 2018-01-01 08:38:11 -08:00
Unknown W. Brackets
905d2c2da6 irjit: Cleanup some invalid op handling. 
And log blocks the same way as other backends.
 2018-01-01 08:38:11 -08:00
Unknown W. Brackets
d8d174fa2b arm64jit: Avoid spilling an extra reg for lwl/lwr. 
It's only needed for swl and swr.
 2018-01-01 08:38:10 -08:00
Unknown W. Brackets
8ffb0101fe jit: Report blocks with uneaten VFPU prefixes. 
There may be options to avoid, like continuing these blocks, especially if
they're likely or something.
 2018-01-01 08:38:10 -08:00
Henrik Rydgård
bf36965410
Merge pull request #10482 from unknownbrackets/irjit 
irjit: Speed up icache block invalidation
 2018-01-01 09:48:54 +01:00