Unknown W. Brackets
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4a93647acb
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riscv: Emit CSR manipulation instructions.
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2022-08-25 21:20:49 -07:00 |
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Unknown W. Brackets
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b5755b6cf7
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riscv: Validate FixupBranch usage better.
Also avoid FixupBranch alignment issues.
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2022-08-25 21:20:49 -07:00 |
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Unknown W. Brackets
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591de6be1d
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riscv: Emit float instructions.
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2022-08-25 21:19:28 -07:00 |
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Unknown W. Brackets
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53693072d2
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riscv: Emit atomic operations.
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2022-08-25 21:19:28 -07:00 |
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Unknown W. Brackets
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c66d02d4db
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riscv: Emit mul/div instructions.
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2022-08-25 21:19:28 -07:00 |
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Unknown W. Brackets
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00280ab2ad
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riscv: Emit fence and 64-bit instructions.
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2022-08-25 21:19:28 -07:00 |
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Unknown W. Brackets
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49ec8a207d
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riscv: Emit 32-bit 3-op instructions, validate GPR.
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2022-08-25 21:19:27 -07:00 |
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Unknown W. Brackets
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1c35cfb325
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riscv: Emit 32-bit load/store and imm ops.
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2022-08-25 21:19:27 -07:00 |
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Unknown W. Brackets
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1dab9d1875
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riscv: Emit standard B/U/J type ops.
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2022-08-25 21:19:27 -07:00 |
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Unknown W. Brackets
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9fcad83940
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riscv: Add initial emitter shell.
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2022-08-25 21:17:11 -07:00 |
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