mirror of
https://github.com/hrydgard/ppsspp.git
synced 2025-04-02 11:01:50 -04:00
riscv: Emit float instructions.
This commit is contained in:
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parent
53693072d2
commit
591de6be1d
2 changed files with 319 additions and 3 deletions
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@ -16,6 +16,7 @@
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// https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
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#include "ppsspp_config.h"
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#include <algorithm>
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#include "Common/RiscVEmitter.h"
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namespace RiscVGen {
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@ -30,6 +31,11 @@ static inline uint8_t BitsSupported() {
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return 64;
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}
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static inline uint8_t FloatBitsSupported() {
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// TODO: 0 if not.
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return 64;
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}
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static inline bool SupportsMulDiv() {
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// TODO
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return true;
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@ -44,15 +50,22 @@ enum class Opcode32 {
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// Note: invalid, just used for FixupBranch.
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ZERO = 0b0000000,
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LOAD = 0b0000011,
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LOAD_FP = 0b0000111,
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MISC_MEM = 0b0001111,
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OP_IMM = 0b0010011,
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AUIPC = 0b0010111,
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OP_IMM_32 = 0b0011011,
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STORE = 0b0100011,
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STORE_FP = 0b0100111,
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AMO = 0b0101111,
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OP = 0b0110011,
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LUI = 0b0110111,
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OP_32 = 0b0111011,
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FMADD = 0b1000011,
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FMSUB = 0b1000111,
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FNMSUB = 0b1001011,
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FNMADD = 0b1001111,
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OP_FP = 0b1010011,
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BRANCH = 0b1100011,
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JALR = 0b1100111,
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JAL = 0b1101111,
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@ -100,10 +113,26 @@ enum class Funct3 {
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DIVU = 0b101,
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REM = 0b110,
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REMU = 0b111,
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FSGNJ = 0b000,
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FSGNJN = 0b001,
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FSGNJX = 0b010,
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FMIN = 0b000,
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FMAX = 0b001,
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FMV = 0b000,
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FCLASS = 0b001,
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FLE = 0b000,
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FLT = 0b001,
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FEQ = 0b010,
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};
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enum class Funct2 {
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// TODO: 0b00,
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S = 0b00,
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D = 0b01,
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Q = 0b11,
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};
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enum class Funct7 {
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@ -127,6 +156,20 @@ enum class Funct5 {
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AMOMAX = 0b10100,
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AMOMINU = 0b11000,
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AMOMAXU = 0b11100,
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FADD = 0b00000,
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FSUB = 0b00001,
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FMUL = 0b00010,
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FDIV = 0b00011,
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FSGNJ = 0b00100,
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FMINMAX = 0b00101,
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FCVT_SZ = 0b01000,
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FSQRT = 0b01011,
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FCMP = 0b10100,
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FCVT_TOX = 0b11000,
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FCVT_FROMX = 0b11010,
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FMV_TOX = 0b11100,
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FMV_FROMX = 0b11110,
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};
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enum class Funct12 {
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@ -158,6 +201,25 @@ static inline u32 EncodeR4(Opcode32 opcode, RiscVReg rd, Funct3 funct3, RiscVReg
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return (u32)opcode | ((u32)DecodeReg(rd) << 7) | ((u32)funct3 << 12) | ((u32)DecodeReg(rs1) << 15) | ((u32)DecodeReg(rs2) << 20) | ((u32)funct2 << 25) | ((u32)DecodeReg(rs3) << 27);
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}
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static inline u32 EncodeFR4(Opcode32 opcode, RiscVReg rd, Funct3 funct3, RiscVReg rs1, RiscVReg rs2, Funct2 funct2, RiscVReg rs3) {
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_assert_msg_(IsFPR(rd), "R4 instruction rd must be FPR");
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_assert_msg_(IsFPR(rs1), "R4 instruction rs1 must be FPR");
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_assert_msg_(IsFPR(rs2), "R4 instruction rs2 must be FPR");
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_assert_msg_(IsFPR(rs3), "R4 instruction rs3 must be FPR");
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return EncodeR4(opcode, rd, funct3, rs1, rs2, funct2, rs3);
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}
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static inline u32 EncodeR(Opcode32 opcode, RiscVReg rd, Funct3 funct3, RiscVReg rs1, RiscVReg rs2, Funct2 funct2, Funct5 funct5) {
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return EncodeR(opcode, rd, funct3, rs1, rs2, (Funct7)(((u32)funct5 << 2) | (u32)funct2));
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}
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static inline u32 EncodeFR(Opcode32 opcode, RiscVReg rd, Funct3 funct3, RiscVReg rs1, RiscVReg rs2, Funct2 funct2, Funct5 funct5) {
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_assert_msg_(IsFPR(rd), "R4 instruction rd must be FPR");
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_assert_msg_(IsFPR(rs1), "R4 instruction rs1 must be FPR");
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_assert_msg_(IsFPR(rs2), "R4 instruction rs2 must be FPR");
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return EncodeR(opcode, rd, funct3, rs1, rs2, (Funct7)(((u32)funct5 << 2) | (u32)funct2));
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}
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static inline u32 EncodeI(Opcode32 opcode, RiscVReg rd, Funct3 funct3, RiscVReg rs1, s32 simm12) {
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_assert_msg_(((simm12 << 20) >> 20) == simm12, "I immediate must be signed s11.0");
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return (u32)opcode | ((u32)DecodeReg(rd) << 7) | ((u32)funct3 << 12) | ((u32)DecodeReg(rs1) << 15) | ((u32)simm12 << 20);
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@ -236,12 +298,13 @@ static inline u32 EncodeGJ(Opcode32 opcode, RiscVReg rd, s32 simm21) {
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return EncodeJ(opcode, rd, simm21);
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}
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static inline Funct3 BitsToFunct3(int bits) {
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static inline Funct3 BitsToFunct3(int bits, bool useFloat = false) {
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int bitsSupported = useFloat ? FloatBitsSupported() : BitsSupported();
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_assert_msg_(bitsSupported >= bits, "Cannot use funct3 width %d, only have %d", bits, bitsSupported);
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switch (bits) {
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case 32:
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return Funct3::LS_W;
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case 64:
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_assert_msg_(BitsSupported() >= 64, "Cannot use funct3 width %d", bits);
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return Funct3::LS_D;
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default:
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_assert_msg_(false, "Invalid funct3 width %d", bits);
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@ -249,6 +312,56 @@ static inline Funct3 BitsToFunct3(int bits) {
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}
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}
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static inline Funct2 BitsToFunct2(int bits) {
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_assert_msg_(FloatBitsSupported() >= bits, "Cannot use funct2 width %d, only have %d", bits, FloatBitsSupported());
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switch (bits) {
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case 32:
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return Funct2::S;
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case 64:
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return Funct2::D;
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case 128:
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return Funct2::Q;
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default:
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_assert_msg_(false, "Invalid funct2 width %d", bits);
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return Funct2::S;
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}
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}
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static inline int FConvToFloatBits(FConv c) {
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switch (c) {
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case FConv::W:
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case FConv::WU:
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case FConv::L:
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case FConv::LU:
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break;
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case FConv::S:
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return 32;
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case FConv::D:
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return 64;
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case FConv::Q:
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return 128;
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}
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return 0;
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}
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static inline int FConvToIntegerBits(FConv c) {
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switch (c) {
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case FConv::S:
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case FConv::D:
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case FConv::Q:
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break;
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case FConv::W:
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case FConv::WU:
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return 32;
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case FConv::L:
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case FConv::LU:
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return 64;
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}
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return 0;
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}
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RiscVEmitter::RiscVEmitter(const u8 *ptr, u8 *writePtr) {
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SetCodePointer(ptr, writePtr);
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}
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@ -838,5 +951,136 @@ void RiscVEmitter::AMOMAXU(int bits, RiscVReg rd, RiscVReg rs2, RiscVReg rs1, At
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Write32(EncodeAtomicR(Opcode32::AMO, rd, BitsToFunct3(bits), rs1, rs2, ordering, Funct5::AMOMAXU));
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}
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void RiscVEmitter::FL(int bits, RiscVReg rd, RiscVReg rs1, s32 simm12) {
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_assert_msg_(IsGPR(rs1) && IsFPR(rd), "FL with incorrect register types");
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Write32(EncodeI(Opcode32::LOAD_FP, rd, BitsToFunct3(bits, true), rs1, simm12));
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}
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void RiscVEmitter::FS(int bits, RiscVReg rs2, RiscVReg rs1, s32 simm12) {
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_assert_msg_(IsGPR(rs1) && IsFPR(rs2), "FS with incorrect register types");
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Write32(EncodeS(Opcode32::STORE_FP, BitsToFunct3(bits, true), rs1, rs2, simm12));
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}
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void RiscVEmitter::FMADD(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, RiscVReg rs3, Round rm) {
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Write32(EncodeFR4(Opcode32::FMADD, rd, (Funct3)rm, rs1, rs2, BitsToFunct2(bits), rs3));
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}
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void RiscVEmitter::FMSUB(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, RiscVReg rs3, Round rm) {
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Write32(EncodeFR4(Opcode32::FMSUB, rd, (Funct3)rm, rs1, rs2, BitsToFunct2(bits), rs3));
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}
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void RiscVEmitter::FNMSUB(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, RiscVReg rs3, Round rm) {
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Write32(EncodeFR4(Opcode32::FNMSUB, rd, (Funct3)rm, rs1, rs2, BitsToFunct2(bits), rs3));
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}
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void RiscVEmitter::FNMADD(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, RiscVReg rs3, Round rm) {
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Write32(EncodeFR4(Opcode32::FNMADD, rd, (Funct3)rm, rs1, rs2, BitsToFunct2(bits), rs3));
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}
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void RiscVEmitter::FADD(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, Round rm) {
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Write32(EncodeFR(Opcode32::OP_FP, rd, (Funct3)rm, rs1, rs2, BitsToFunct2(bits), Funct5::FADD));
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}
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void RiscVEmitter::FSUB(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, Round rm) {
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Write32(EncodeFR(Opcode32::OP_FP, rd, (Funct3)rm, rs1, rs2, BitsToFunct2(bits), Funct5::FSUB));
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}
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void RiscVEmitter::FMUL(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, Round rm) {
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Write32(EncodeFR(Opcode32::OP_FP, rd, (Funct3)rm, rs1, rs2, BitsToFunct2(bits), Funct5::FMUL));
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}
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void RiscVEmitter::FDIV(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, Round rm) {
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Write32(EncodeFR(Opcode32::OP_FP, rd, (Funct3)rm, rs1, rs2, BitsToFunct2(bits), Funct5::FDIV));
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}
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void RiscVEmitter::FSQRT(int bits, RiscVReg rd, RiscVReg rs1, Round rm) {
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Write32(EncodeFR(Opcode32::OP_FP, rd, (Funct3)rm, rs1, F0, BitsToFunct2(bits), Funct5::FSQRT));
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}
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void RiscVEmitter::FSGNJ(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2) {
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Write32(EncodeFR(Opcode32::OP_FP, rd, Funct3::FSGNJ, rs1, rs2, BitsToFunct2(bits), Funct5::FSGNJ));
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}
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void RiscVEmitter::FSGNJN(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2) {
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Write32(EncodeFR(Opcode32::OP_FP, rd, Funct3::FSGNJN, rs1, rs2, BitsToFunct2(bits), Funct5::FSGNJ));
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}
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void RiscVEmitter::FSGNJX(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2) {
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Write32(EncodeFR(Opcode32::OP_FP, rd, Funct3::FSGNJX, rs1, rs2, BitsToFunct2(bits), Funct5::FSGNJ));
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}
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void RiscVEmitter::FMIN(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2) {
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Write32(EncodeFR(Opcode32::OP_FP, rd, Funct3::FMIN, rs1, rs2, BitsToFunct2(bits), Funct5::FMINMAX));
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}
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void RiscVEmitter::FMAX(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2) {
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Write32(EncodeFR(Opcode32::OP_FP, rd, Funct3::FMAX, rs1, rs2, BitsToFunct2(bits), Funct5::FMINMAX));
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}
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void RiscVEmitter::FCVT(FConv to, FConv from, RiscVReg rd, RiscVReg rs1, Round rm) {
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int floatBits = std::max(FConvToFloatBits(from), FConvToFloatBits(to));
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int integerBits = std::max(FConvToIntegerBits(from), FConvToIntegerBits(to));
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_assert_msg_(floatBits > 0, "FCVT can't be used with only GPRs");
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_assert_msg_(integerBits <= BitsSupported(), "FCVT for %d integer bits, only %d supported", integerBits, BitsSupported());
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_assert_msg_(floatBits <= FloatBitsSupported(), "FCVT for %d float bits, only %d supported", floatBits, FloatBitsSupported());
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if (integerBits == 0) {
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// Convert between float widths.
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Funct2 fromFmt = BitsToFunct2(FConvToFloatBits(from));
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Funct2 toFmt = BitsToFunct2(FConvToFloatBits(to));
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Write32(EncodeR(Opcode32::OP_FP, rd, (Funct3)rm, rs1, (RiscVReg)fromFmt, toFmt, Funct5::FCVT_SZ));
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} else {
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Funct5 funct5 = FConvToIntegerBits(to) == 0 ? Funct5::FCVT_FROMX : Funct5::FCVT_TOX;
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FConv integerFmt = FConvToIntegerBits(to) == 0 ? from : to;
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Funct2 floatFmt = BitsToFunct2(floatBits);
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_assert_msg_(((int)integerFmt & ~3) == 0, "Got wrong integer bits");
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Write32(EncodeR(Opcode32::OP_FP, rd, (Funct3)rm, rs1, (RiscVReg)integerFmt, floatFmt, funct5));
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}
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}
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void RiscVEmitter::FMV(FMv to, FMv from, RiscVReg rd, RiscVReg rs1) {
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int bits = 0;
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switch (to == FMv::X ? from : to) {
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case FMv::D: bits = 64; break;
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case FMv::W: bits = 32; break;
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case FMv::X: bits = 0; break;
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}
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_assert_msg_(BitsSupported() >= bits && FloatBitsSupported() >= bits, "FMV cannot be used for %d bits, only %d/%d supported", bits, BitsSupported(), FloatBitsSupported());
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_assert_msg_((to == FMv::X && from != FMv::X) || (to != FMv::X && from == FMv::X), "%s can only transfer between FPR/GPR", __func__);
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_assert_msg_(to == FMv::X ? IsGPR(rd) : IsFPR(rd), "%s rd of wrong type", __func__);
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_assert_msg_(from == FMv::X ? IsGPR(rs1) : IsFPR(rs1), "%s rs1 of wrong type", __func__);
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Funct5 funct5 = to == FMv::X ? Funct5::FMV_TOX : Funct5::FMV_FROMX;
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Write32(EncodeR(Opcode32::OP_FP, rd, Funct3::FMV, rs1, F0, BitsToFunct2(bits), funct5));
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}
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void RiscVEmitter::FEQ(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2) {
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_assert_msg_(IsGPR(rd), "%s rd must be GPR", __func__);
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_assert_msg_(IsFPR(rs1), "%s rs1 must be FPR", __func__);
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_assert_msg_(IsFPR(rs2), "%s rs2 must be FPR", __func__);
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Write32(EncodeR(Opcode32::OP_FP, rd, Funct3::FEQ, rs1, rs2, BitsToFunct2(bits), Funct5::FCMP));
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}
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void RiscVEmitter::FLT(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2) {
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_assert_msg_(IsGPR(rd), "%s rd must be GPR", __func__);
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_assert_msg_(IsFPR(rs1), "%s rs1 must be FPR", __func__);
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_assert_msg_(IsFPR(rs2), "%s rs2 must be FPR", __func__);
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Write32(EncodeR(Opcode32::OP_FP, rd, Funct3::FLT, rs1, rs2, BitsToFunct2(bits), Funct5::FCMP));
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}
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void RiscVEmitter::FLE(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2) {
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_assert_msg_(IsGPR(rd), "%s rd must be GPR", __func__);
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_assert_msg_(IsFPR(rs1), "%s rs1 must be FPR", __func__);
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_assert_msg_(IsFPR(rs2), "%s rs2 must be FPR", __func__);
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Write32(EncodeR(Opcode32::OP_FP, rd, Funct3::FLE, rs1, rs2, BitsToFunct2(bits), Funct5::FCMP));
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}
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void RiscVEmitter::FCLASS(int bits, RiscVReg rd, RiscVReg rs1) {
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_assert_msg_(IsGPR(rd), "%s rd must be GPR", __func__);
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_assert_msg_(IsFPR(rs1), "%s rs1 must be FPR", __func__);
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Write32(EncodeR(Opcode32::OP_FP, rd, Funct3::FCLASS, rs1, F0, BitsToFunct2(bits), Funct5::FMV_TOX));
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}
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};
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@ -64,6 +64,32 @@ enum class Atomic {
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SEQUENTIAL = 0b11,
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};
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enum class Round {
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NEAREST_EVEN = 0b000,
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TOZERO = 0b001,
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DOWN = 0b010,
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UP = 0b011,
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NEAREST_MAX = 0b100,
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DYNAMIC = 0b111,
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};
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enum class FConv {
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W = 0x0000,
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WU = 0x0001,
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L = 0x0002,
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LU = 0x0003,
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S = 0x1000,
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D = 0x1001,
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Q = 0x1003,
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};
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enum class FMv {
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X,
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W,
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D,
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};
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struct FixupBranch {
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FixupBranch(const u8 *p, FixupBranchType t) : ptr(p), type(t) {}
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@ -224,6 +250,52 @@ public:
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void AMOMINU(int bits, RiscVReg rd, RiscVReg rs2, RiscVReg addr, Atomic ordering);
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void AMOMAXU(int bits, RiscVReg rd, RiscVReg rs2, RiscVReg addr, Atomic ordering);
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// Floating point (same funcs for single/double/quad, if supported.)
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void FL(int bits, RiscVReg rd, RiscVReg addr, s32 simm12);
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void FS(int bits, RiscVReg rs2, RiscVReg addr, s32 simm12);
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void FLW(RiscVReg rd, RiscVReg addr, s32 simm12) {
|
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FL(32, rd, addr, simm12);
|
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}
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void FSW(RiscVReg rs2, RiscVReg addr, s32 simm12) {
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||||
FS(32, rs2, addr, simm12);
|
||||
}
|
||||
|
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void FMADD(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, RiscVReg rs3, Round rm = Round::DYNAMIC);
|
||||
void FMSUB(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, RiscVReg rs3, Round rm = Round::DYNAMIC);
|
||||
void FNMSUB(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, RiscVReg rs3, Round rm = Round::DYNAMIC);
|
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void FNMADD(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, RiscVReg rs3, Round rm = Round::DYNAMIC);
|
||||
|
||||
void FADD(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, Round rm = Round::DYNAMIC);
|
||||
void FSUB(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, Round rm = Round::DYNAMIC);
|
||||
void FMUL(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, Round rm = Round::DYNAMIC);
|
||||
void FDIV(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2, Round rm = Round::DYNAMIC);
|
||||
void FSQRT(int bits, RiscVReg rd, RiscVReg rs1, Round rm = Round::DYNAMIC);
|
||||
|
||||
void FSGNJ(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
|
||||
void FSGNJN(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
|
||||
void FSGNJX(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
|
||||
|
||||
void FMV(int bits, RiscVReg rd, RiscVReg rs) {
|
||||
FSGNJ(bits, rd, rs, rs);
|
||||
}
|
||||
void FNEG(int bits, RiscVReg rd, RiscVReg rs) {
|
||||
FSGNJN(bits, rd, rs, rs);
|
||||
}
|
||||
void FABS(int bits, RiscVReg rd, RiscVReg rs) {
|
||||
FSGNJX(bits, rd, rs, rs);
|
||||
}
|
||||
|
||||
void FMIN(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
|
||||
void FMAX(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
|
||||
|
||||
void FCVT(FConv to, FConv from, RiscVReg rd, RiscVReg rs1, Round rm = Round::DYNAMIC);
|
||||
void FMV(FMv to, FMv from, RiscVReg rd, RiscVReg rs1);
|
||||
|
||||
void FEQ(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
|
||||
void FLT(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
|
||||
void FLE(int bits, RiscVReg rd, RiscVReg rs1, RiscVReg rs2);
|
||||
void FCLASS(int bits, RiscVReg rd, RiscVReg rs1);
|
||||
|
||||
private:
|
||||
void SetJumpTarget(const FixupBranch &branch, const void *dst);
|
||||
bool BInRange(const void *src, const void *dst) const;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue