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10357 commits 81 branches 122 tags 700 MiB
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36 commits

Author SHA1 Message Date
Henrik Rydgard
06ce01ea04 Remove erroneous comment. 2013-11-09 17:34:52 +01:00
Henrik Rydgard
5ad04a23f4 x86 jit: Rename BindToRegister to MapReg 2013-11-09 15:23:31 +01:00
Henrik Rydgard
316d23d4cc Optimize mfv/mtv/mfc1/mtc1 on x86 too 2013-11-09 14:06:45 +01:00
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cbf1df9b01 Check for nan/inf in trunc.w.s in x86 jit. 
Now x86 jit passes the fpu test too.
 2013-09-13 22:32:25 -07:00
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97aa1a631e Improve typesafety in the x86 regalloc. 2013-08-24 19:41:10 -07:00
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109ad17ac6 Use a typesafe struct for opcodes. 
Also, correctly read delayslots using Read_Instruction on ARM.
 2013-08-24 15:36:24 -07:00
Henrik Rydgard
89ddbb51bb Oops, XMM0 might be taken by temps. Also, s/GC_ALIGN16/MEMORY_ALIGN16 2013-08-10 23:39:24 +02:00
Henrik Rydgard
2f0cdc6988 ARMJIT: disable vi2f, it seems buggy. preliminary disabled impl of vcrsp.t. 2013-08-06 11:10:26 +02:00
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2d6a730cac Add some basics for memory checks to x86 jit. 
Specifically, we will need to be able to bail in delayslots,
and we will need to know the size of the access (useful anyway.)
 2013-03-09 02:41:46 -08:00
Henrik Rydgard
e32721c72a Merge branch 'master' into armjit-fpu 
Conflicts:
	Core/MIPS/MIPSVFPUUtils.cpp
	Core/MIPS/x86/CompVFPU.cpp
	GPU/GLES/VertexDecoder.cpp
 2013-02-19 00:50:33 +01:00
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0fdc975fde Fix wrong type in x86 jit fpu/vfpu load store. 2013-02-16 20:22:08 -08:00
Henrik Rydgard
44e4ba8772 Merge branch 'master' into armjit-fpu 2013-02-15 21:42:44 +01:00
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f6f2927526 Add curlies around DISABLE/CONDITIONAL_DISABLE. 2013-02-15 08:35:33 -08:00
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abe390e6f3 Add some checks for fpu/vfpu writing to $0. 2013-02-14 00:27:09 -08:00
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4789a8e5eb Oops, can't have CONDITIONAL_DISABLE here, no op. 2013-02-14 00:27:08 -08:00
Henrik Rydgard
30318a4a4d Merge branch 'master' into armjit-fpu 
Conflicts:
	Core/MIPS/x86/CompFPU.cpp
 2013-02-13 20:47:41 +01:00
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f1386dfca1 Add a quick optimization to the x86 fpu comps. 2013-02-13 02:21:26 -08:00
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19cc652a37 Correct NaN handling in fpu comparisons. 2013-02-13 01:54:07 -08:00
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3cab6986c5 Jit the FPU comparisons on x86. 
Probably not too fast.  Also, NaN handling seems wrong?
 2013-02-13 00:55:10 -08:00
Henrik Rydgard
2c01b36585 Some FPU optimization 2013-02-12 00:58:31 +01:00
Henrik Rydgard
3a11b030d6 Merge branch 'master' into armjit-fpu 
Conflicts:
	Core/MIPS/ARM/ArmCompFPU.cpp
	Core/MIPS/x86/CompFPU.cpp
 2013-02-10 15:57:16 +01:00
Henrik Rydgard
f75d14d3b5 ARM FPU jit work 2013-02-10 15:53:56 +01:00
Henrik Rydgard
78923f5538 Jit a little more (vfpu single load/store, transfer instructions) 2013-02-10 12:14:55 +01:00
Henrik Rydgard
377c94b125 JIT x86: cvt.s.w 2013-02-06 20:29:49 +01:00
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b77ce99d01 Oops, no slow read for immediates usually. 2013-01-26 09:27:52 -08:00
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9cd5836b85 Rename WriteFinish() to Finish() is safe mem. 
It's nothing to do with writing.
 2013-01-26 09:09:47 -08:00
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3e419f513a Refactor jit safe memory reads without dup code. 
But, maybe too automagical...
 2013-01-26 08:42:34 -08:00
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b7ef3e7bef Make sure to log / check bad immediate mem access. 
Although, theoretically, this should never happen.
Also, definitely time to refactor.
 2013-01-25 23:06:43 -08:00
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3418383917 Immediately break on bad mem access in jit slowmem. 2013-01-25 22:52:51 -08:00
Henrik Rydgard
68991511ee Split out the FPU reg cache into its own file too. 2013-01-26 01:34:19 +01:00
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a43078ab68 Same optimization for FPU load / store. 2013-01-20 13:16:41 -08:00
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da22eb8adf Make swc1 and lwc1 fast even without fastmem. 2013-01-20 02:07:00 -08:00
Henrik Rydgard
f5efd6f2b1 JIT: add option to enable/disable jit of memory instructions. for crash safety. 2012-12-21 16:50:13 +01:00
Henrik Rydgard
d485b76e11 Jit fixes, test update 2012-11-12 14:35:10 +01:00
Henrik Rydgard
64cc573703 Switch to "GPL 2.0 or later" for various reasons. I wrote most of the code I imported from Dolphin (which is GPL2-but-not-later), so it should be OK. 2012-11-04 23:24:00 +01:00
Henrik Rydgard
4f7ad15758 Add snapshot of the whole source code. 2012-11-01 16:19:01 +01:00