35 commits

Author	SHA1	Message	Date
Unknown W. Brackets	97aa1a631e	Improve typesafety in the x86 regalloc.	2013-08-24 19:41:10 -07:00
Unknown W. Brackets	109ad17ac6	Use a typesafe struct for opcodes. ... Also, correctly read delayslots using Read_Instruction on ARM.	2013-08-24 15:36:24 -07:00
Unknown W. Brackets	3278b5e373	Handle the immediate case of clz/clo.	2013-07-04 23:07:42 -07:00
Unknown W. Brackets	654490566f	Implement clz/clo in x86 jit.	2013-07-04 18:01:17 -07:00
Sacha	a26b48fc0b	Stub wsbh/wsbw for x86.	2013-06-05 14:55:01 +10:00
Unknown W. Brackets	028e85dc92	Cleanup some differences between the two jits.	2013-03-07 02:08:44 -08:00
Unknown W. Brackets	313ffdb495	Add a stub for clz/clo in x86 jit.	2013-02-21 01:25:02 -08:00
Unknown W. Brackets	08923c092b	Implement ins and ext in the x86 jit.	2013-02-21 01:25:01 -08:00
Unknown W. Brackets	dede852c03	Optimize out slti in the x86 jit. ... I'm kinda surprised this actually happens...	2013-02-21 01:25:01 -08:00
Unknown W. Brackets	abde404c00	Optimize out some addu/etc. calls against imms.	2013-02-21 01:25:01 -08:00
Unknown W. Brackets	9e479b4391	Optimize addi/addiu to just LEA when possible.	2013-02-21 01:25:00 -08:00
Unknown W. Brackets	2db368c29a	Add more imm handling for shifts in x86 jit. ... This is actually hit, and propagates more imms through.	2013-02-21 01:25:00 -08:00
Unknown W. Brackets	958d95a029	Make bitrev use less instructions in the x86 jit. ... Much less.	2013-02-20 13:43:17 -08:00
Unknown W. Brackets	7b612cf28d	Don't need this with the imm code path.	2013-02-20 12:16:57 -08:00
Unknown W. Brackets	c8f85ace41	Implement bitrev in x86 jit + some imms.	2013-02-20 12:09:02 -08:00
Unknown W. Brackets	c3be50acbb	Implement movz/movn in the x86 jit.	2013-02-20 12:09:01 -08:00
Unknown W. Brackets	0d6d58fed4	Add min and max to the x86 jit portfolio.	2013-02-20 12:09:01 -08:00
Unknown W. Brackets	f6f2927526	Add curlies around DISABLE/CONDITIONAL_DISABLE.	2013-02-15 08:35:33 -08:00
Unknown W. Brackets	7c428bfeba	Fix immediate div CMP.	2013-02-10 10:02:55 -08:00
Unknown W. Brackets	e0ebfd2211	Jit div/divu in x86.	2013-02-10 09:36:41 -08:00
Unknown W. Brackets	9bb78ce2ec	Jit madd/msub in x86.	2013-02-10 08:45:35 -08:00
Henrik Rydgard	78923f5538	Jit a little more (vfpu single load/store, transfer instructions)	2013-02-10 12:14:55 +01:00
Unknown W. Brackets	6bee870ac9	Fix CompShiftVar for x86 jit. ... In case rd == rs, need to load ECX first. I can't find anything else wrong with it for it to be disabled.	2013-02-02 14:02:07 -08:00
Henrik Rydgard	90b11bba37	Implement mult, multu, mflo/hi, mtlo/hi in x86 JIT	2013-01-29 00:48:42 +01:00
Unknown W. Brackets	db5fa233a8	Make sure we don't mark a reg dirty on noop.	2013-01-25 22:34:01 -08:00
Henrik Rydgard	2738417040	VFPU JIT: start setting up infrastructure. very incomplete. vdot works if undisabled, but isn't complete.	2013-01-26 01:34:19 +01:00
Unknown W. Brackets	a7c6f46829	Optimize and/or 0 to just a mov in x86 jit.	2013-01-25 00:25:40 -08:00
Unknown W. Brackets	ab9bea068c	Jit reg+reg compile time, and avoid flushing EDX.	2013-01-25 00:16:55 -08:00
Unknown W. Brackets	ce5f393fb8	Hit immediates in the ALU better and more simply.	2013-01-25 00:16:55 -08:00
Henrik Rydgard	f326c36220	Some cleanup, re-enable some apparently disabled jit ops	2012-11-18 23:14:22 +01:00
Henrik Rydgard	7720dc3f60	Various warning, logging, jit fixes	2012-11-17 19:56:28 +01:00
Henrik Rydgard	d485b76e11	Jit fixes, test update	2012-11-12 14:35:10 +01:00
Henrik Rydgard	9bc7385502	Power test working	2012-11-11 19:32:27 +01:00
Henrik Rydgard	64cc573703	Switch to "GPL 2.0 or later" for various reasons. I wrote most of the code I imported from Dolphin (which is GPL2-but-not-later), so it should be OK.	2012-11-04 23:24:00 +01:00
Henrik Rydgard	4f7ad15758	Add snapshot of the whole source code.	2012-11-01 16:19:01 +01:00