Commit graph

653 commits

Author SHA1 Message Date
Henrik Rydgård
bfffe33438 Merge pull request #6469 from unknownbrackets/logging
Enforce semicolons at the end of log lines
2014-06-30 11:44:02 +02:00
Unknown W. Brackets
433f4eb00a Use the ARM rounding mode flag for conversions.
It's at least much simpler.  Not sure if faster.  Handles NAN correctly.
2014-06-29 20:36:00 -07:00
Unknown W. Brackets
f339f7d539 armjit: Handle NAN correctly in float conversion. 2014-06-29 20:05:59 -07:00
Unknown W. Brackets
c168db5943 armjit: Fix really bad typo in cvt.w.s. 2014-06-29 19:43:17 -07:00
Unknown W. Brackets
0078faef8b Fix some log semicolons that might affect logic.
But, these should all be right.
2014-06-29 19:09:38 -07:00
Unknown W. Brackets
5db79dcf11 Fix some missing semicolons on log statements. 2014-06-29 19:09:37 -07:00
Unknown W. Brackets
252100aee5 Remove outdated comment (real cause found/fixed.) 2014-06-28 16:06:10 -07:00
Unknown W. Brackets
f008bebab4 armjit: Fix floor/ceil/cvt.w.s rounding.
Unfortunately, correctly rounding is probably slower.
2014-06-28 00:38:57 -07:00
Unknown W. Brackets
f544a87b2f jit: Initialize startDefaultPrefix when switching. 2014-06-28 00:38:56 -07:00
Unknown W. Brackets
bc3d789c8a x86jit: Cache the vfpu compare flags in a reg.
Again, to match armjit.
2014-06-28 00:38:55 -07:00
Unknown W. Brackets
acad2e1763 x86jit: Cache fpcond in a register.
Mostly to match armjit.
2014-06-28 00:38:55 -07:00
Unknown W. Brackets
24d8a34a0b Properly respect resolveReplacements.
And use the same opcode reading func in armjit as x86jit.
Fixes Star Ocean on Android.
2014-06-23 08:20:38 -07:00
Unknown W. Brackets
d7e2c2c1d2 armjit: Oops, correctly handle plus/minus vmin/max. 2014-06-21 07:45:47 -07:00
Unknown W. Brackets
62daf6d7c8 armjit: Fix vmin/vmax to follow the PSP's rules.
Also the interpreter.  Fixes #6107.
2014-06-20 23:55:33 -07:00
Unknown W. Brackets
e87e1606c5 Fix func replacements and delay slots on arm.
Fixes #6303.
2014-06-19 08:02:49 -07:00
Unknown W. Brackets
9efbc2694b Add an invalidate all method to the jit. 2014-06-19 01:13:06 -07:00
Henrik Rydgard
0879d76503 VFPU: Ensure that sin(4*x) returns 0.0 (and cos 1) for all x. Fixes #2921 2014-06-15 11:03:00 +02:00
Sacha
55221b5c7c Sin/cos fix for hardfp builds. 2014-06-12 23:10:22 +10:00
Henrik Rydgård
fd19b8d271 Merge pull request #6197 from unknownbrackets/replace-funcs
Function replacement hooks and some GLES compat replacements
2014-05-31 20:30:30 +02:00
Unknown W. Brackets
5ccc227462 armjit: Minor const optimization in Comp_VV2Op. 2014-05-31 11:12:36 -07:00
Unknown W. Brackets
df289e46a9 armjit: Use sat0/1 method from prefixes in vsat. 2014-05-31 11:12:35 -07:00
Unknown W. Brackets
d09be5a4bc Update PC before going into a replacement func.
This way we can report the PC properly on errors, and the replacement func
can even look at PC.
2014-05-31 10:03:01 -07:00
Unknown W. Brackets
f489694515 Add the option to hook, rather than replace, funcs.
This can be useful for debugging or developing translations/game hacks,
and also gives us options when dealing with GLES incompatibilities.
2014-05-31 10:03:00 -07:00
Unknown W. Brackets
69b0b622be armjit: Fix D-prefix sat clamp NAN handling.
They should leave NAN alone.
2014-05-16 01:04:57 -07:00
Unknown W. Brackets
bc32f0e0b2 armjit: Correct disabled vslt NaN handling.
Can possibly enable?
2014-05-16 01:04:57 -07:00
The Dax
086d97516d Fix a couple ARM VFPU flags.
Unknown's explanation:
LO means Lower (unsigned), but for floats, it means "Less than".
LT means Lower (signed), but for floats it means "Less than OR unordered".
ARM docs at http://infocenter.arm.com/help/topic/com.arm.doc.dui0068b/Chdhcfbc.html explain the following:
LE means Signed less than or equal, and for floats it means "Less than or equal, or unordered".
LS means Unsigned lower or same, but for floats, it means "Less than or equal"
2014-05-04 22:37:41 -04:00
Unknown W. Brackets
3001866d18 Skip flushing FPU/VFPU regs if none were allocated.
They're not used as often, so this usually saves time.  About 1% during
tests.
2014-03-30 00:42:25 -07:00
Unknown W. Brackets
a4327702f1 Reduce some includes under GPU/. 2014-03-29 16:51:38 -07:00
Henrik Rydgård
717c1cd34e Merge pull request #5748 from unknownbrackets/armjit-minor
armjit: Allow R1 in regalloc, use LR as temp
2014-03-29 04:09:58 -04:00
Unknown W. Brackets
600842d9a2 armjit: Use prefixes on vscl's T arg.
Makes it pass one more thing in the prefixes test, but not sure exactly
how it operates.  Better to have it the same as x86 and int anyway.
2014-03-29 01:00:29 -07:00
Unknown W. Brackets
5a89c17cf0 armjit: Allow R1 in regalloc, use LR as temp.
LR should be safe, although it may make stack traces not work within jit,
they don't really tend to work anyway.
2014-03-28 18:38:38 -07:00
Unknown W. Brackets
58c5179d8e Push and pop the callee saved NEON registers. 2014-03-25 22:34:42 -07:00
Unknown W. Brackets
2f5c6a5660 Fix VLDM/VSTM encoding for double/quad regs.
Duh, forgot to check Vd.  Fixes #5723.
2014-03-25 22:08:20 -07:00
Unknown W. Brackets
b53143bb33 Revert "armjit: Skip an AND for rotate shifts."
This reverts commit ab2dd54ade.

Even though the docs say it's safe but apparently not always.
2014-03-22 15:54:48 -07:00
Henrik Rydgård
98165b599f Merge pull request #5653 from unknownbrackets/armjit-minor
Minor armjit optimizations, fix B/BL encoding
2014-03-22 16:05:59 +01:00
Unknown W. Brackets
05ab192c9c Reduce includes in Core/HLE/.
Especially templates.
2014-03-15 11:22:19 -07:00
Henrik Rydgard
c80510fb3b MemMap should not be included in MIPS.h. 2014-03-15 10:45:39 +01:00
Unknown W. Brackets
ab2dd54ade armjit: Skip an AND for rotate shifts. 2014-03-15 00:49:18 -07:00
Unknown W. Brackets
bed9c82d0a armjit: Try to use nearby immediates in slti/u. 2014-03-14 19:26:52 -07:00
Unknown W. Brackets
e783627947 armjit: Use our I2R funcs on reg/reg math too.
When one is a known immediate.  This should catch more cases, like:

ori v0, $0, 0xFFFF
and v1, v1, v0
2014-03-14 19:15:43 -07:00
Unknown W. Brackets
8e979da0f9 armjit: Use our I2R arm optimizations.
Should help cases of ori and andi most, but also addiu.  They will all try
to use an optimized immediate (from another nearby value) if possible.
2014-03-14 19:15:43 -07:00
Unknown W. Brackets
c229232236 armjit: Specifically optimize check for negative. 2014-03-14 19:15:39 -07:00
Unknown W. Brackets
628390f3fa armjit: Tiny optimization for cast to short.
See these sometimes in code, skip the load of R0 when we can.
2014-03-14 19:15:39 -07:00
Unknown W. Brackets
ca0a8d0269 armjit: fix lwl/lwr from an imm address.
Can't skip loading the reg value.  Likely cause of #5057, possibly other
bugs as well.
2014-03-13 00:23:00 -07:00
Henrik Rydgard
174b5187e6 Arm VFPU: 2-op and 3-op: map registers before work, improving instruction order a little. 2014-03-12 11:06:26 +01:00
Henrik Rydgard
7ae9c26b6a Enable the new vreg flushing mechanism on ARM.
Reduce logspam seen in a couple games.
2014-03-12 10:15:09 +01:00
Henrik Rydgard
ea6fb9337c Second attempt at flushing multiple VFPU regs using VSTMIA.
Also disabled, but seems to work, just needs testing.

Much better code this time and works for VFPU regs not just FPU regs.
2014-03-11 21:55:17 +01:00
Henrik Rydgard
adadf11890 An attempt to combine FPU regcache writebacks with VSTMIA. Disabled due to bugs. 2014-03-11 11:03:51 +01:00
Sacha
30a6a5d10f ARMJIT: Implement VLDM/VSTM load/store combinations and use in armjit. Also add them to disassembler. 2014-03-07 02:56:34 +10:00
Henrik Rydgård
b2260149ae ARM Jit: Avoid materializing some unnecessary immediates in loads/stores 2014-03-03 14:33:22 +01:00