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37 commits

Author SHA1 Message Date
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88b6442527 irjit: Add facility for native reg transfer. 2023-09-24 16:28:29 -07:00
Henrik Rydgård
2f300c2023
Merge pull request #18060 from unknownbrackets/x86-jitbase 
x86jit: Bake emuhack mask into jitbase
 2023-09-03 22:53:23 +02:00
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1d152a1486 x86jit: Bake emuhack mask into jitbase. 2023-09-03 12:49:36 -07:00
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1b756ff8c1 arm64jit: Add initial base for IR jit. 
This works, but very slowly at this point.
 2023-09-03 12:14:28 -07:00
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4b1c809886 x86jit: Implement a few more float ops, shuffle. 2023-08-27 23:24:30 -07:00
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07fa1ed573 x86jit: Automatically flush incompatible regs. 2023-08-21 21:16:54 -07:00
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db34b85107 irjit: Allow flag-based allocation order. 
Sometimes backends have needs, like XMM0/v0-only, or similar.
 2023-08-21 20:46:05 -07:00
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36b6aa4728 riscv: Allow GPR "SIMD" without FPR SIMD. 2023-08-20 12:42:11 -07:00
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6a75e6712e riscv: Use automapping for special cases too. 2023-08-20 12:42:11 -07:00
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a190793ad2 riscv: Simplify mapping for more instructions. 2023-08-20 12:42:11 -07:00
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cc4bc406d5 riscv: Cleanup VfpuCtrlToReg meta, use auto-map. 2023-08-20 12:42:11 -07:00
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e40ae60029 riscv: Mark normalized32 after mapping. 
It's less confusing to separate it.
 2023-08-20 12:42:11 -07:00
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f9bf7de701 riscv: Use a single reg cache. 2023-08-20 12:42:11 -07:00
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e30fb82a64 riscv: Remove some unused reg funcs. 2023-08-20 12:42:11 -07:00
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a23ade8f75 riscv: Map IR regs based on metadata. 
Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
 2023-08-20 12:42:11 -07:00
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161465ab66 riscv: Centralize register FlushAll(). 2023-08-19 21:30:03 -07:00
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f3d4bd8c11 riscv: Centralize reg-as-pointer. 2023-08-19 21:24:36 -07:00
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92f7374c89 riscv: Centralize reg mapping itself. 2023-08-19 16:15:49 -07:00
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718a1b3944 riscv: Centralize MarkDirty flagging. 2023-08-19 16:15:49 -07:00
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4e41f83ecc riscv: Centralize IR reg cache metadata checks. 
These are all largely the same between backends.
 2023-08-17 23:03:31 -07:00
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ebab0e1591 riscv: Centralize reg allocation. 2023-08-17 18:50:33 -07:00
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b30daa5760 riscv: Centralize state of regcaches. 2023-08-15 21:51:38 -07:00
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b03398a46c
Merge pull request #17815 from unknownbrackets/riscv-jit 
riscv: Spill registers more intelligently
 2023-07-30 14:49:37 -07:00
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f870271011 riscv: Spill registers more intelligently. 2023-07-30 14:24:12 -07:00
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5ef4b2b5fa riscv: Fix assert when flushing not mapped reg. 2023-07-30 14:19:28 -07:00
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c24e3ef831 riscv: Implement ll/sc. 2023-07-30 00:45:51 -07:00
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067a033dc0 riscv: Add FPU regcache. 2023-07-25 20:33:56 -07:00
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b97b7f3663 riscv: Make some regcache methods private. 2023-07-25 19:42:04 -07:00
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b6f83ca969 riscv: Cleanup some pointerification flags. 2023-07-23 21:17:55 -07:00
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2c7da94bd1 riscv: Implement shifts and compares. 2023-07-23 18:01:00 -07:00
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94be343591 riscv: Try to keep regs normalized, track. 
Since we can't address the lower 32-bits only in compares, this can help
us avoid renormalizing before a compare.
 2023-07-23 18:01:00 -07:00
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8ee73264bf riscv: Correct depointerify on FlushAll(). 2023-07-23 18:01:00 -07:00
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720f868a10 riscv: Use R_RA as a temporary for calls. 
This is the most logical thing, since we're about to write it anyway.
 2023-07-23 18:01:00 -07:00
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d31eded9ba riscv: Allow dirty pointers, explicitly. 2023-07-23 18:01:00 -07:00
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165169eb31 riscv: Implement load and store ops. 2023-07-23 18:01:00 -07:00
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c6c25af484 riscv: Add some safety to pointerifying. 
We have to clear the upper bits in case of sign extension or other things.
 2023-07-23 18:01:00 -07:00
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4c1cc2dfdc riscv: Add a register cache for jit. 
Not yet actually used.  Might be buggy.
 2023-07-23 18:01:00 -07:00