Emulation/ppsspp
1
0
Fork 0
mirror of https://github.com/hrydgard/ppsspp.git synced 2025-04-02 11:01:50 -04:00
Code Issues Projects Releases Packages Wiki Activity
42256 commits 81 branches 122 tags 700 MiB
Commit graph

27 commits

Author SHA1 Message Date
Unknown W. Brackets
88b6442527 irjit: Add facility for native reg transfer. 2023-09-24 16:28:29 -07:00
Unknown W. Brackets
1b756ff8c1 arm64jit: Add initial base for IR jit. 
This works, but very slowly at this point.
 2023-09-03 12:14:28 -07:00
Unknown W. Brackets
4b1c809886 x86jit: Implement a few more float ops, shuffle. 2023-08-27 23:24:30 -07:00
Unknown W. Brackets
07fa1ed573 x86jit: Automatically flush incompatible regs. 2023-08-21 21:16:54 -07:00
Unknown W. Brackets
db34b85107 irjit: Allow flag-based allocation order. 
Sometimes backends have needs, like XMM0/v0-only, or similar.
 2023-08-21 20:46:05 -07:00
Unknown W. Brackets
6a75e6712e riscv: Use automapping for special cases too. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets
a190793ad2 riscv: Simplify mapping for more instructions. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets
cc4bc406d5 riscv: Cleanup VfpuCtrlToReg meta, use auto-map. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets
e40ae60029 riscv: Mark normalized32 after mapping. 
It's less confusing to separate it.
 2023-08-20 12:42:11 -07:00
Unknown W. Brackets
f9bf7de701 riscv: Use a single reg cache. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets
e30fb82a64 riscv: Remove some unused reg funcs. 2023-08-20 12:42:11 -07:00
Unknown W. Brackets
a23ade8f75 riscv: Map IR regs based on metadata. 
Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.
 2023-08-20 12:42:11 -07:00
Unknown W. Brackets
161465ab66 riscv: Centralize register FlushAll(). 2023-08-19 21:30:03 -07:00
Unknown W. Brackets
92f7374c89 riscv: Centralize reg mapping itself. 2023-08-19 16:15:49 -07:00
Unknown W. Brackets
718a1b3944 riscv: Centralize MarkDirty flagging. 2023-08-19 16:15:49 -07:00
Unknown W. Brackets
4e41f83ecc riscv: Centralize IR reg cache metadata checks. 
These are all largely the same between backends.
 2023-08-17 23:03:31 -07:00
Unknown W. Brackets
ebab0e1591 riscv: Centralize reg allocation. 2023-08-17 18:50:33 -07:00
Unknown W. Brackets
b30daa5760 riscv: Centralize state of regcaches. 2023-08-15 21:51:38 -07:00
Unknown W. Brackets
f870271011 riscv: Spill registers more intelligently. 2023-07-30 14:24:12 -07:00
Unknown W. Brackets
6b632a103d riscv: Implement FSin/similar. 2023-07-29 19:02:15 -07:00
Unknown W. Brackets
067a033dc0 riscv: Add FPU regcache. 2023-07-25 20:33:56 -07:00
Unknown W. Brackets
b97b7f3663 riscv: Make some regcache methods private. 2023-07-25 19:42:04 -07:00
Unknown W. Brackets
94be343591 riscv: Try to keep regs normalized, track. 
Since we can't address the lower 32-bits only in compares, this can help
us avoid renormalizing before a compare.
 2023-07-23 18:01:00 -07:00
Unknown W. Brackets
d31eded9ba riscv: Allow dirty pointers, explicitly. 2023-07-23 18:01:00 -07:00
Unknown W. Brackets
c6c25af484 riscv: Add some safety to pointerifying. 
We have to clear the upper bits in case of sign extension or other things.
 2023-07-23 18:01:00 -07:00
Unknown W. Brackets
4c1cc2dfdc riscv: Add a register cache for jit. 
Not yet actually used.  Might be buggy.
 2023-07-23 18:01:00 -07:00
Unknown W. Brackets
47b81985bd riscv: Initial untested dispatcher. 
The minimum to actually, probably, running code.  Pretty slow.
 2023-07-23 18:01:00 -07:00