16 commits

Author	SHA1	Message	Date
Unknown W. Brackets	7d0f2e43b6	irjit: Fix safety of kernel bit memory addresses.	2023-09-24 10:18:55 -07:00
Unknown W. Brackets	85b80bc9e5	arm64jit: Implement load/store in IR.	2023-09-04 00:04:36 -07:00
Unknown W. Brackets	e40ae60029	riscv: Mark normalized32 after mapping. ... It's less confusing to separate it.	2023-08-20 12:42:11 -07:00
Unknown W. Brackets	f9bf7de701	riscv: Use a single reg cache.	2023-08-20 12:42:11 -07:00
Unknown W. Brackets	a23ade8f75	riscv: Map IR regs based on metadata. ... Only doing this in places without GPR/FPR mix or FPR/Vec overlap for now.	2023-08-20 12:42:11 -07:00
Unknown W. Brackets	4e41f83ecc	riscv: Centralize IR reg cache metadata checks. ... These are all largely the same between backends.	2023-08-17 23:03:31 -07:00
Unknown W. Brackets	7cc6c5fa62	riscv: Fix load error w/o pointerify.	2023-08-13 10:20:28 -07:00
Unknown W. Brackets	93e3d35f5d	irjit: Move more to IRNativeBackend, split.	2023-08-06 00:16:43 -07:00
Unknown W. Brackets	c24e3ef831	riscv: Implement ll/sc.	2023-07-30 00:45:51 -07:00
Unknown W. Brackets	df2462b1d9	irjit: Implement ll/sc. ... These occur more than I expected in LittleBigPlanet while loading.	2023-07-29 17:57:44 -07:00
Unknown W. Brackets	4e17c59cc2	riscv: Implement simple vec4 ops via floats.	2023-07-25 20:33:56 -07:00
Unknown W. Brackets	bb6fdd0246	riscv: Add floating point load/stores.	2023-07-25 20:33:56 -07:00
Unknown W. Brackets	94be343591	riscv: Try to keep regs normalized, track. ... Since we can't address the lower 32-bits only in compares, this can help us avoid renormalizing before a compare.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	165169eb31	riscv: Implement load and store ops.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	c2da7d18bb	riscv: Stub out more IR compilation categories.	2023-07-23 18:01:00 -07:00
Unknown W. Brackets	bf7a6eb2cd	riscv: Add jit for some initial instructions.	2023-07-23 18:01:00 -07:00