From e5dabaabe2a68169934d15ccd7934a4b709e2539 Mon Sep 17 00:00:00 2001
From: "Unknown W. Brackets" <checkins@unknownbrackets.org>
Date: Wed, 26 Nov 2014 09:20:50 -0800
Subject: [PATCH] x86jit: Optimize simd->non for 1-lane a little.

---
 Core/MIPS/x86/RegCacheFPU.cpp | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Core/MIPS/x86/RegCacheFPU.cpp b/Core/MIPS/x86/RegCacheFPU.cpp
index 4b2bfef0e1..c4c4734e78 100644
--- a/Core/MIPS/x86/RegCacheFPU.cpp
+++ b/Core/MIPS/x86/RegCacheFPU.cpp
@@ -420,8 +420,12 @@ void FPURegCache::SimpleRegsV(const u8 *v, MatrixSize msz, int flags) {
 }
 
 void FPURegCache::SimpleRegV(const u8 v, int flags) {
-	const MIPSCachedFPReg &vr = vregs[v];
-	if (vr.lane != 0) {
+	MIPSCachedFPReg &vr = vregs[v];
+	// Special optimization: if it's in a single simd, we can keep it there.
+	if (vr.lane == 1 && xregs[VSX(v)].mipsRegs[1] == -1) {
+		// Just change the lane to 0.
+		vr.lane = 0;
+	} else if (vr.lane != 0) {
 		// This will never end up in a register this way, so ignore dirty.
 		if ((flags & MAP_NOINIT)) {
 			// This will discard only this reg, and store the others.