From e4f9c72fe9b01cc984dbfa7538ebad5babad2ddb Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sun, 16 Jul 2023 16:20:58 -0700 Subject: [PATCH] riscv: Avoid unaligned mem combine in IR. --- Core/MIPS/IR/IRJit.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Core/MIPS/IR/IRJit.cpp b/Core/MIPS/IR/IRJit.cpp index 5b882c2d5f..6a82ec1f7c 100644 --- a/Core/MIPS/IR/IRJit.cpp +++ b/Core/MIPS/IR/IRJit.cpp @@ -15,6 +15,7 @@ // Official git repository and contact information can be found at // https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. +#include "ppsspp_config.h" #include #include "ext/xxhash.h" @@ -49,7 +50,10 @@ IRJit::IRJit(MIPSState *mipsState) : frontend_(mipsState->HasDefaultPrefix()), m IROptions opts{}; opts.disableFlags = g_Config.uJitDisableFlags; + // Assume that RISC-V always has very slow unaligned memory accesses. +#if !PPSSPP_ARCH(RISCV64) opts.unalignedLoadStore = (opts.disableFlags & (uint32_t)JitDisable::LSU_UNALIGNED) == 0; +#endif frontend_.SetOptions(opts); }