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Add more reporting for cpu instructions.

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Unknown W. Brackets 2013-09-05 23:27:51 -07:00
parent efe92666fb
commit dc05051696
2 changed files with 4 additions and 2 deletions
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4
Core/MIPS/MIPSIntVFPU.cpp
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@ -1365,6 +1365,7 @@ namespace MIPSInt
}
else
{
Reporting::ReportMessage("Trying to interpret instruction that can't be interpreted (BADVTFM)");
_dbg_assert_msg_(CPU,0,"Trying to interpret instruction that can't be interpreted (BADVTFM)");
}
WriteVector(d, sz, vd);
@ -1675,7 +1676,7 @@ namespace MIPSInt
}
else
{
_dbg_assert_msg_(CPU,0,"Bad Imm3 in cmov");
ERROR_LOG_REPORT(CPU, "Bad Imm3 in cmov: %d", imm3);
}
ApplyPrefixD(d, sz);
WriteVector(d, sz, vd);
@ -1756,6 +1757,7 @@ bad:
break;
default:
Reporting::ReportMessage("CrossQuat instruction with wrong size");
_dbg_assert_msg_(CPU,0,"Trying to interpret instruction that can't be interpreted");
break;
}

2
Core/MIPS/x86/CompBranch.cpp
View file

@ -466,7 +466,7 @@ void Jit::BranchVFPUFlag(MIPSOpcode op, Gen::CCFlags cc, bool likely)
if (!likely && delaySlotIsNice)
CompileDelaySlot(DELAYSLOT_NICE);
if (delaySlotIsBranch && (signed short)(delaySlotOp & 0xFFFF) != (signed short)(op & 0xFFFF) - 1)
ERROR_LOG(JIT, "VFPU branch in VFPU delay slot at %08x with different target %d / %d", js.compilerPC, (signed short)(delaySlotOp & 0xFFFF), (signed short)(op & 0xFFFF) - 1);
ERROR_LOG_REPORT(JIT, "VFPU branch in VFPU delay slot at %08x with different target %d / %d", js.compilerPC, (signed short)(delaySlotOp & 0xFFFF), (signed short)(op & 0xFFFF) - 1);
// THE CONDITION
int imm3 = (op >> 18) & 7;