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https://github.com/hrydgard/ppsspp.git
synced 2025-04-02 11:01:50 -04:00
Log more info about branches in delay slots.
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0a4cd1b82a
commit
c9c3bc83e4
2 changed files with 12 additions and 12 deletions
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@ -53,7 +53,7 @@ namespace MIPSComp
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void Jit::BranchRSRTComp(u32 op, ArmGen::CCFlags cc, bool likely)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x", js.compilerPC);
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ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = (signed short)(op&0xFFFF)<<2;
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@ -113,7 +113,7 @@ void Jit::BranchRSRTComp(u32 op, ArmGen::CCFlags cc, bool likely)
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void Jit::BranchRSZeroComp(u32 op, ArmGen::CCFlags cc, bool andLink, bool likely)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in RSZeroComp delay slot at %08x", js.compilerPC);
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ERROR_LOG_REPORT(JIT, "Branch in RSZeroComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = (signed short)(op&0xFFFF)<<2;
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@ -208,7 +208,7 @@ void Jit::Comp_RelBranchRI(u32 op)
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void Jit::BranchFPFlag(u32 op, ArmGen::CCFlags cc, bool likely)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in FPFlag delay slot at %08x", js.compilerPC);
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ERROR_LOG_REPORT(JIT, "Branch in FPFlag delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = (signed short)(op & 0xFFFF) << 2;
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@ -266,7 +266,7 @@ void Jit::Comp_FPUBranch(u32 op)
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void Jit::BranchVFPUFlag(u32 op, ArmGen::CCFlags cc, bool likely)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in VFPU delay slot at %08x", js.compilerPC);
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ERROR_LOG_REPORT(JIT, "Branch in VFPU delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = (signed short)(op & 0xFFFF) << 2;
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@ -326,7 +326,7 @@ void Jit::Comp_VBranch(u32 op)
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void Jit::Comp_Jump(u32 op)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in Jump delay slot at %08x", js.compilerPC);
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ERROR_LOG_REPORT(JIT, "Branch in Jump delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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u32 off = ((op & 0x03FFFFFF) << 2);
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@ -358,7 +358,7 @@ void Jit::Comp_Jump(u32 op)
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void Jit::Comp_JumpReg(u32 op)
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{
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in JumpReg delay slot at %08x", js.compilerPC);
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ERROR_LOG_REPORT(JIT, "Branch in JumpReg delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int rs = _RS;
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@ -129,7 +129,7 @@ void Jit::BranchRSRTComp(u32 op, Gen::CCFlags cc, bool likely)
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{
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CONDITIONAL_LOG;
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x", js.compilerPC);
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ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = (signed short)(op&0xFFFF)<<2;
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@ -185,7 +185,7 @@ void Jit::BranchRSZeroComp(u32 op, Gen::CCFlags cc, bool andLink, bool likely)
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{
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CONDITIONAL_LOG;
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in RSZeroComp delay slot at %08x", js.compilerPC);
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ERROR_LOG_REPORT(JIT, "Branch in RSZeroComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = (signed short)(op&0xFFFF)<<2;
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@ -280,7 +280,7 @@ void Jit::BranchFPFlag(u32 op, Gen::CCFlags cc, bool likely)
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{
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CONDITIONAL_LOG;
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in FPFlag delay slot at %08x", js.compilerPC);
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ERROR_LOG_REPORT(JIT, "Branch in FPFlag delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = (signed short)(op & 0xFFFF) << 2;
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@ -341,7 +341,7 @@ void Jit::BranchVFPUFlag(u32 op, Gen::CCFlags cc, bool likely)
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{
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CONDITIONAL_LOG;
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in VFPU delay slot at %08x", js.compilerPC);
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ERROR_LOG_REPORT(JIT, "Branch in VFPU delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int offset = (signed short)(op & 0xFFFF) << 2;
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@ -405,7 +405,7 @@ void Jit::Comp_Jump(u32 op)
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{
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CONDITIONAL_LOG;
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in Jump delay slot at %08x", js.compilerPC);
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ERROR_LOG_REPORT(JIT, "Branch in Jump delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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u32 off = ((op & 0x3FFFFFF) << 2);
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@ -442,7 +442,7 @@ void Jit::Comp_JumpReg(u32 op)
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{
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CONDITIONAL_LOG;
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if (js.inDelaySlot) {
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ERROR_LOG_REPORT(JIT, "Branch in JumpReg delay slot at %08x", js.compilerPC);
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ERROR_LOG_REPORT(JIT, "Branch in JumpReg delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart);
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return;
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}
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int rs = _RS;
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