From c9c3bc83e4d33fdfe812ebfa9cc83af1a2de1aa4 Mon Sep 17 00:00:00 2001 From: "Unknown W. Brackets" Date: Sun, 30 Jun 2013 13:19:27 -0700 Subject: [PATCH] Log more info about branches in delay slots. --- Core/MIPS/ARM/ArmCompBranch.cpp | 12 ++++++------ Core/MIPS/x86/CompBranch.cpp | 12 ++++++------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/Core/MIPS/ARM/ArmCompBranch.cpp b/Core/MIPS/ARM/ArmCompBranch.cpp index 419b0a13c7..0b2bf2b553 100644 --- a/Core/MIPS/ARM/ArmCompBranch.cpp +++ b/Core/MIPS/ARM/ArmCompBranch.cpp @@ -53,7 +53,7 @@ namespace MIPSComp void Jit::BranchRSRTComp(u32 op, ArmGen::CCFlags cc, bool likely) { if (js.inDelaySlot) { - ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x", js.compilerPC); + ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); return; } int offset = (signed short)(op&0xFFFF)<<2; @@ -113,7 +113,7 @@ void Jit::BranchRSRTComp(u32 op, ArmGen::CCFlags cc, bool likely) void Jit::BranchRSZeroComp(u32 op, ArmGen::CCFlags cc, bool andLink, bool likely) { if (js.inDelaySlot) { - ERROR_LOG_REPORT(JIT, "Branch in RSZeroComp delay slot at %08x", js.compilerPC); + ERROR_LOG_REPORT(JIT, "Branch in RSZeroComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); return; } int offset = (signed short)(op&0xFFFF)<<2; @@ -208,7 +208,7 @@ void Jit::Comp_RelBranchRI(u32 op) void Jit::BranchFPFlag(u32 op, ArmGen::CCFlags cc, bool likely) { if (js.inDelaySlot) { - ERROR_LOG_REPORT(JIT, "Branch in FPFlag delay slot at %08x", js.compilerPC); + ERROR_LOG_REPORT(JIT, "Branch in FPFlag delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); return; } int offset = (signed short)(op & 0xFFFF) << 2; @@ -266,7 +266,7 @@ void Jit::Comp_FPUBranch(u32 op) void Jit::BranchVFPUFlag(u32 op, ArmGen::CCFlags cc, bool likely) { if (js.inDelaySlot) { - ERROR_LOG_REPORT(JIT, "Branch in VFPU delay slot at %08x", js.compilerPC); + ERROR_LOG_REPORT(JIT, "Branch in VFPU delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); return; } int offset = (signed short)(op & 0xFFFF) << 2; @@ -326,7 +326,7 @@ void Jit::Comp_VBranch(u32 op) void Jit::Comp_Jump(u32 op) { if (js.inDelaySlot) { - ERROR_LOG_REPORT(JIT, "Branch in Jump delay slot at %08x", js.compilerPC); + ERROR_LOG_REPORT(JIT, "Branch in Jump delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); return; } u32 off = ((op & 0x03FFFFFF) << 2); @@ -358,7 +358,7 @@ void Jit::Comp_Jump(u32 op) void Jit::Comp_JumpReg(u32 op) { if (js.inDelaySlot) { - ERROR_LOG_REPORT(JIT, "Branch in JumpReg delay slot at %08x", js.compilerPC); + ERROR_LOG_REPORT(JIT, "Branch in JumpReg delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); return; } int rs = _RS; diff --git a/Core/MIPS/x86/CompBranch.cpp b/Core/MIPS/x86/CompBranch.cpp index bfa8315c09..f224ac695c 100644 --- a/Core/MIPS/x86/CompBranch.cpp +++ b/Core/MIPS/x86/CompBranch.cpp @@ -129,7 +129,7 @@ void Jit::BranchRSRTComp(u32 op, Gen::CCFlags cc, bool likely) { CONDITIONAL_LOG; if (js.inDelaySlot) { - ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x", js.compilerPC); + ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); return; } int offset = (signed short)(op&0xFFFF)<<2; @@ -185,7 +185,7 @@ void Jit::BranchRSZeroComp(u32 op, Gen::CCFlags cc, bool andLink, bool likely) { CONDITIONAL_LOG; if (js.inDelaySlot) { - ERROR_LOG_REPORT(JIT, "Branch in RSZeroComp delay slot at %08x", js.compilerPC); + ERROR_LOG_REPORT(JIT, "Branch in RSZeroComp delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); return; } int offset = (signed short)(op&0xFFFF)<<2; @@ -280,7 +280,7 @@ void Jit::BranchFPFlag(u32 op, Gen::CCFlags cc, bool likely) { CONDITIONAL_LOG; if (js.inDelaySlot) { - ERROR_LOG_REPORT(JIT, "Branch in FPFlag delay slot at %08x", js.compilerPC); + ERROR_LOG_REPORT(JIT, "Branch in FPFlag delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); return; } int offset = (signed short)(op & 0xFFFF) << 2; @@ -341,7 +341,7 @@ void Jit::BranchVFPUFlag(u32 op, Gen::CCFlags cc, bool likely) { CONDITIONAL_LOG; if (js.inDelaySlot) { - ERROR_LOG_REPORT(JIT, "Branch in VFPU delay slot at %08x", js.compilerPC); + ERROR_LOG_REPORT(JIT, "Branch in VFPU delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); return; } int offset = (signed short)(op & 0xFFFF) << 2; @@ -405,7 +405,7 @@ void Jit::Comp_Jump(u32 op) { CONDITIONAL_LOG; if (js.inDelaySlot) { - ERROR_LOG_REPORT(JIT, "Branch in Jump delay slot at %08x", js.compilerPC); + ERROR_LOG_REPORT(JIT, "Branch in Jump delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); return; } u32 off = ((op & 0x3FFFFFF) << 2); @@ -442,7 +442,7 @@ void Jit::Comp_JumpReg(u32 op) { CONDITIONAL_LOG; if (js.inDelaySlot) { - ERROR_LOG_REPORT(JIT, "Branch in JumpReg delay slot at %08x", js.compilerPC); + ERROR_LOG_REPORT(JIT, "Branch in JumpReg delay slot at %08x in block starting at %08x", js.compilerPC, js.blockStart); return; } int rs = _RS;