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riscv: Add detect flags, not detected yet.

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Unknown W. Brackets 2023-12-01 22:40:27 -08:00
parent e5467d2706
commit 83dc1c9705
3 changed files with 14 additions and 8 deletions
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5
Common/CPUDetect.h
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@ -114,6 +114,11 @@ struct CPUInfo {
bool RiscV_Zbb;
bool RiscV_Zbc;
bool RiscV_Zbs;
bool RiscV_Zcb;
bool RiscV_Zfa;
bool RiscV_Zfh;
bool RiscV_Zfhmin;
bool RiscV_Zicond;
// LoongArch specific extension flags.
bool LOONGARCH_CPUCFG;

5
Common/RiscVCPUDetect.cpp
View file

@ -245,6 +245,11 @@ std::vector<std::string> CPUInfo::Features() {
{ RiscV_Zbb, "Bitmanip Zbb" },
{ RiscV_Zbc, "Bitmanip Zbc" },
{ RiscV_Zbs, "Bitmanip Zbs" },
{ RiscV_Zcb, "Compress Zcb" },
{ RiscV_Zfa, "Float Additional" },
{ RiscV_Zfh, "Float Half" },
{ RiscV_Zfhmin, "Float Half Minimal" },
{ RiscV_Zicond, "Integer Conditional" },
{ RiscV_Zicsr, "Zicsr" },
{ CPU64bit, "64-bit" },
};

12
Common/RiscVEmitter.cpp
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@ -32,8 +32,7 @@ static inline bool SupportsCompressed(char zcx = '\0') {
return false;
switch (zcx) {
// TODO: cpu_info.RiscV_Zcb
case 'b': return false;
case 'b': return cpu_info.RiscV_Zcb;
case '\0': return true;
default: return false;
}
@ -79,18 +78,15 @@ static inline bool SupportsBitmanip(char zbx) {
}
static inline bool SupportsIntConditional() {
// TODO: cpu_info.RiscV_Zicond;
return false;
return cpu_info.RiscV_Zicond;
}
static inline bool SupportsFloatHalf(bool allowMin = false) {
// TODO
return false;
return cpu_info.RiscV_Zfh || (cpu_info.RiscV_Zfhmin && allowMin);
}
static inline bool SupportsFloatExtra() {
// TODO: cpu_info.RiscV_Zfa
return false;
return cpu_info.RiscV_Zfa;
}
enum class Opcode32 {